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Technical Training from World’s No. 1 AMD ATP 2023

PLC2 Training Courses Around FPGAs, SoCs, MPSoCs, Programming Languages, and More

We at PLC2 provide first-class expert training classes addressing today’s engineering challenges.

 

Advanced technologies, tools and methodologies for FPGAs and embedded systems are developing at a lighting pace.  How do you deal with all these new development opportunities created by state of the art technologies?

PLC2 is the Expert Authorized Training Provider partner for AMD. We provide training around embedded solutions with core competencies in FPGA technologies. We have trained 1000s of engineers across the world thanks to the inhouse knowledge we developed over the last 30 years.

 

Choose the training format that suits you, a 2-day course, an intensive long-term training, or on the job consulting. PLC2 is your partner for your next challenge.

The PLC2 Training
Offering Is Divided
into the Following
6 Categories:

All Trainings

Course Format Category Location Duration Date

All about Memories in Adaptive SoCs

WE (Webinar)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

1 hour

on demand

Info

adaptive SoC memory programming FPGA AMD webinar, Memories, Memory, UltraRAM, BlockRAM, Memory Access, Adaptive SoC

VHDL Circuit Simulation Part 2: Stimulus Generation and Behavior Verification

WE (Webinar)

Programming Languages

Online

11-12 am CEST

Jul 23, 2024

Info

VHDL circuit simulation simulations FPGA AMD webinar

VHDL Circuit Simulation Part 1: Behavior Modeling, Timing, and File I/O

WE (Webinar)

Programming Languages

Online

1 hour

on demand

Info

VHDL circuit simulation simulations FPGA AMD webinar

VHDL Circuit Design Part 2: Advanced Concepts and Behavioral Modeling

WE (Webinar)

Programming Languages

Online

1 hour

on demand

Info

VHDL circuit design designs application applications behavioral modeling AMD webinar

VHDL Circuit Design Part 1: Fundamentals and Methodologies

WE (Webinar)

Programming Languages

Online

1 hour

on demand

Info

VHDL circuit design designs application applications AMD webinar HDL hardware design

FPGA Timing Constraints: A Comprehensive Overview

WE (Webinar)

Development
Tools & Methodology

Online

1 hour

on demand

Info

FPGA timing constraints AMD Vivado AMD FPGA design flow virtual clocks webinar

Mastering Clock Domain Crossing: Strategies for Synchronization and Stability

WE (Webinar)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Online

1 hour

on demand

Info

clock domain crossing AMDF FPGA FPGAs metastability synchronizers MTBF signal synchronization AMD webinar

FPGA Circuit Design Part 2: Interfaces and Best Practices

WE (Webinar)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Online

1 hour

on demand

Info

FPGA Circuit Design designs synchronous asynchronous design techniques technique designing state machines machine AMD webinar

FPGA Circuit Design Part 1: Synchronous and Asynchronous Design Techniques

WE (Webinar)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Online

1 hour

on demand

Info

FPGA Circuit Design designs synchronous asynchronous design techniques technique, designing state machines machine AMD

Versal Adaptive SoC from Ground Up: Application Level Design Support

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

1 day

Jan 16, 2025

Info

Versal Adaptive SoC from Ground Up: System Level Design and AI Engines

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

1 day

Oct 31, 2024

Info

Versal Adaptive SoC from Ground Up: Basic Design Flow

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

1 day

Sep 26, 2024

Info

Developing Demanding Applications with Versal Adaptive SoCs

OL (Online Live)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Online

1 day

the whole year tbd

Info

Seminar Versal Adaptive SoC Vitis Unififed Development Platform design integration

Microservice Applications on Versal and Other Adaptive SoCs

WE (Webinar)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

1 hour

on demand

Info

Fast Track Evaluation of ML Models on Versal Adaptive SoC

WE (Webinar)

DSP & Image Processing

Online

1 hour

on demand

Info

Multimedia Accelerators for Kria SoM with HLS & Vitis Libraries

WE (Webinar)

Development
Tools & Methodology

Online

1 hour

on demand

Info

Acceleration Kernels with Versal AI Engine

WE (Webinar)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

1 hour

on demand

Info

Versal, AI Engine, ACAP, Acceleration Kernel, Kernels, Kernel, Acceleration

Understanding Versal: The Adaptable Engines

WE (Webinar)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Online

1 hour

on demand

Info

Versal, AI, Zynq, MPSoC

Understanding Versal: The DSP Engines

WE (Webinar)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Online

1 hour

on demand

Info

Versal, AI, Zynq, MPSoC

Understanding Versal: The AI Engine

WE (Webinar)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Online

1 hour

on demand

Info

Versal, AI, Zynq, MPSoC

Understanding Versal: Scalar Engines – The Processing System

WE (Webinar)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Online

1 hour

on demand

Info

Versal, AI, Zynq, MPSoC

Understanding Versal: The Architecture

WE (Webinar)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Online

1 hour

on demand

Info

Versal, AI, Zynq, MPSoC

Understanding Versal: Versal vs. Zynq MPSoC

WE (Webinar)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Online

1 hour

on demand

Info

Versal, AI, Zynq, MPSoC

Versal Adaptive SoC: The Processing System Interfaces

WE (Webinar)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

1 hour

on demand

Info

Versal, AI, Ultrascale+, MPSoC

Vitis Tools for Acceleration – Creating a RTL Kernel: From HDL to Reusable Packaged Kernel

WE (Webinar)

Development
Tools & Methodology

Online

1 hour

on demand

Info

Vitis, RTL kernel, acceleration, design flow

Embedded Device Driver Management in Vitis

WE (Webinar)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

1 hour

on demand

Info

Versal, AI, webinar, framework, debugger

Partially Constrained Record Types in VHDL-2008 Or: How to Wire Components Effectively?

WE (Webinar)

Programming Languages

Online

1 hour

on demand

Info

VHDL, VHDL-2008, partially constrained types

Vitis – Huge Debugging Varieties

WE (Webinar)

Development
Tools & Methodology

Online

1 hour

on demand

Info

Versal, AI, webinar, framework, debugger

Vitis AI – Creating an Edge Inference Solution – FPGA-Based Deep Learning (DNN) Accelerator

WE (Webinar)

Development
Tools & Methodology

Online

1 hour

on demand

Info

Vitis AI – Whole  Application Acceleration Using Versal VCK190

WE (Webinar)

Development
Tools & Methodology

Online

1 hour

on demand

Info

Introduction to ROS Video Application Acceleration Using Kria SOM and Vitis Tools

WE (Webinar)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

1 hour

on demand

Info

ROS, Kria SOM, Vitis, MPSoC

Introduction to AI Applications Using Kria SoM

WE (Webinar)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

1 hour

on demand

Info

Vitis Model Composer for Kria SoM: Block Diagram Based Accelerator Design

WE (Webinar)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

1 hour

on demand

Info

Vivado IPI – Increase the Productivity in Hardware Design

WE (Webinar)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

1 hour

on demand

Info

NEW | Scripting the AMD Hardware Design Flow Using Vivado

OL (Online Live)

Development
Tools & Methodology

Online

3 days

Oct 28, 2024

Info

NEW | Scripting the AMD Hardware Design Flow Using Vivado

OL (Online Live)

Development
Tools & Methodology

Online

3 days

Dec 16, 2024

Info

NEW | Scripting the AMD Hardware Design Flow Using Vivado

WO (Workshop)

Development
Tools & Methodology

Frankfurt / Main

3 days

Sep 25, 2024

Info

NEW | Scripting the AMD Hardware Design Flow Using Vivado

WO (Workshop)

Development
Tools & Methodology

Stuttgart

3 days

Nov 13, 2024

Info

Circuit Synthesis with VHDL

SE (Seminar)

Programming Languages

Stuttgart

1 day

Oct 15, 2024

Info

FPGA HDL VHDL HDL Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream

Circuit Simulation with VHDL

SE (Seminar)

Programming Languages

Frankfurt / Main

1 day

Nov 13, 2024

Info

FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation

Compact SystemVerilog for Synthesis

WO (Workshop)

Programming Languages

Munich

3 days

Oct 07, 2024

Info

FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis

Compact SystemVerilog for Synthesis

OL (Online Live)

Programming Languages

Online

3 days

Nov 27, 2024

Info

FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis

NEW | Easy Start ML Application Design Flow

ES (Easy Start)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Stuttgart

2 days

Oct 23, 2024

Info

Easy Start ML Application Design Flow Machine Learning Vitis AI AMD adaptive SoCs AMD adaptive SoC Deep Learning Processing Unit DPU PyTorch TensorFlow

NEW | Easy Start ML Application Design Flow

ES (Easy Start)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Munich

2 days

Dec 05, 2024

Info

Easy Start ML Application Design Flow Machine Learning Vitis AI AMD adaptive SoCs AMD adaptive SoC Deep Learning Processing Unit DPU PyTorch TensorFlow

Easy Start Embedded Flow

ES (Easy Start)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

2 days

Sep 09, 2024

Info

Easy Start Embedded AMD programmable platforms adaptive SoCs adaptive SoC FPGA FPGAs processor core Vivado Vitis c c++ c/c++ AMD FPGAs and adaptive SoCs technology programming languages VHDL AXI hardware design

Easy Start Embedded Flow

ES (Easy Start)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Stuttgart

2 days

Nov 11, 2024

Info

Easy Start Embedded AMD programmable platforms adaptive SoCs adaptive SoC FPGA FPGAs processor core Vivado Vitis c c++ c/c++ AMD FPGAs and adaptive SoCs technology programming languages VHDL AXI hardware design

Compact Verilog

WO (Workshop)

Programming Languages

3 days

all year on request

Info

FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis

Compact Verilog

OL (Online Live)

Programming Languages

3 days

all year on request

Info

FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis

Advanced VHDL

OL (Online Live)

Programming Languages

Online

3 days

Dec 16, 2024

Info

Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool

Advanced VHDL

WO (Workshop)

Programming Languages

Freiburg

3 days

Oct 28, 2024

Info

Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool

Advanced VHDL

WO (Workshop)

Programming Languages

Munich

3 days

Dec 09, 2024

Info

Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool

Compact MicroBlaze System Design

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

3 days

all year on request

Info

Embedded MicroBlaze System Design Systems FPGA hardware software AMD tool tools custom peripheral application debugging integration microprocessor microprocessors Vivado Vitis

Compact MicroBlaze System Design

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

3 days

all year on request

Info

Embedded MicroBlaze System Design Systems FPGA hardware software AMD tool tools custom peripheral application debugging integration microprocessor microprocessors Vivado Vitis

Compact VHDL Testbenches and Verification with OSVVM

WO (Workshop)

Programming Languages

Berlin

3 days

Aug 06, 2024

Info

FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator

Compact VHDL Testbenches and Verification with OSVVM

WO (Workshop)

Programming Languages

Munich

3 days

Oct 16, 2024

Info

FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator

Compact VHDL Testbenches and Verification with OSVVM

OL (Online Live)

Programming Languages

Online

3 days

Dec 09, 2024

Info

FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator

Advanced Vivado

WO (Workshop)

Development
Tools & Methodology

Frankfurt / Main

3 days

Oct 28, 2024

Info

Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog

Advanced Vivado

OL (Online Live)

Development
Tools & Methodology

Online

3 days

Oct 28, 2024

Info

Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog

Compact Versal Adaptive SoC: PCI Express Systems

WO (Workshop)

Connectivity

Stuttgart

2 days

Oct 14, 2024

Info

Versal PCI Express Integrated Block for PCI Express Gen4 PL PCIe CPM PCIe High-Speed Interfaces Transceiver DDR4 PCB Design PCB Simulation ACAP PCIe endpoint root port DMA VCK190

Compact Versal Adaptive SoC: PCI Express Systems

OL (Online Live)

Connectivity

Online

2 days

Nov 21, 2024

Info

Versal PCI Express Integrated Block for PCI Express Gen4 PL PCIe CPM PCIe High-Speed Interfaces Transceiver DDR4 PCB Design PCB Simulation ACAP PCIe endpoint root port DMA VCK190

Kria for the Software Developer

SE (Seminar)

Embedded for AMD (Adaptive) SoCs & MPSoCs

1 day

all year on request

Info

SoM Acceleration Vitis tool flow Zynq MPSoC Software C

Professional Versal Adaptive SoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

5 days

Sep 02, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI

Professional Versal Adaptive SoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Stuttgart

5 days

Nov 11, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI

Professional Versal Adaptive SoC

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

5 days

Nov 11, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI

Compact Zynq 7000 SoC for the Software Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

3 days

all year on request

Info

Embedded Architecture Vivado Vitis SoC Cortex-A9 Processor Cache PetaLinux Linux PS AXI

Compact Zynq 7000 SoC for the Software Designer

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

3 days

all year on request

Info

Embedded Architecture Vivado Vitis SoC Cortex-A9 Processor Cache PetaLinux Linux PS AXI

Professional Zynq 7000 SoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

5 days

all year on request

Info

Embedded Architecture Vivado Vitis Zynq SoC Boot Software C C++ AXI Configuration System Integration Debugging AXI

Professional Zynq 7000 SoC

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

5 days

all year on request

Info

Embedded Architecture Vivado Vitis Zynq SoC Boot Software C C++ AXI Configuration System Integration Debugging AXI

Professional Zynq UltraScale+ MPSoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

5 days

Sep 16, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Professional Zynq UltraScale+ MPSoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

5 days

Dec 02, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Professional Zynq UltraScale+ MPSoC

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

5 days

Dec 02, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Professional MicroBlaze System Design

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

5 days

all year on request

Info

Embedded Vitis softcore driver c c++ Vivado processor microcontroller core MicroBlaze Architecture Cache Workflow Platform AXI Peripherals Vivado

Professional MicroBlaze System Design

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

5 days

all year on request

Info

Embedded Vitis softcore driver c c++ Vivado processor microcontroller core MicroBlaze Architecture Cache Workflow Platform AXI Peripherals Vivado

Expert Zynq 7000 SoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

5 days

all year on request

Info

Embedded Architecture Vivado Vitis SoC Cortex-A9 Processor Cache PetaLinux IP-Integrator Linux PS AXI

Expert Zynq 7000 SoC

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

5 days

all year on request

Info

Embedded Architecture Vivado Vitis SoC Cortex-A9 Processor Cache PetaLinux IP-Integrator Linux PS AXI

Expert Versal Adaptive SoC AI Engine

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

5 days

Oct 07, 2024

Info

Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP , Acceleration & AI

Expert Versal Adaptive SoC AI Engine

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

5 days

Oct 07, 2024

Info

Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP , Acceleration & AI

Embedded Linux Driver Development

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

3 days

Aug 05, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Driver Character Yocto tool flow Zynq

Embedded Linux Driver Development

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

3 days

Oct 16, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Driver Character Yocto tool flow Zynq

Embedded Linux Driver Development

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

3 days

Oct 16, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Driver Character Yocto tool flow Zynq

Embedded Design with PetaLinux Tools

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

2 days

Sep 11, 2024

Info

Embedded Linux PetaLinux build rootfs kernel driver layer DeviceTree Device-Tree Boot

Embedded Design with PetaLinux Tools

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Munich

2 days

Nov 28, 2024

Info

Embedded Linux PetaLinux build rootfs kernel driver layer DeviceTree Device-Tree Boot

Embedded Design with PetaLinux Tools

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

2 days

Nov 28, 2024

Info

Embedded Linux PetaLinux build rootfs kernel driver layer DeviceTree Device-Tree Boot

Easy Start Kria for Vision Development

ES (Easy Start)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

2 days

Sep 23, 2024

Info

SOM Vision Vivado Vitis AI Kria Image Processing Vision Kernel Rootfs DeviceTree Device-Tree Embedded mulitmedia camera PetaLinux Linux easy start

Easy Start Kria for Vision Development

ES (Easy Start)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

2 days

Nov 05, 2024

Info

SOM Vision Vivado Vitis AI Kria Image Processing Vision Kernel Rootfs DeviceTree Device-Tree Embedded mulitmedia camera PetaLinux Linux easy start

Easy Start Embedded PetaLinux

ES (Easy Start)

Embedded for AMD (Adaptive) SoCs & MPSoCs

2 days

all year on request

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Rootfs Zynq easy start

Easy Start Embedded for Zynq-7000 SoC Systems

ES (Easy Start)

Embedded for AMD (Adaptive) SoCs & MPSoCs

2 days

all year on request

Info

Embedded Introduction Beginner Overview Zynq SoC Embedded Software C C++ Einführung Einstieg bit Bitstream Vivado Vitis AXI Cortex-A9 Processor DSP PS Software Development easy start

Easy Start Embedded for Zynq UltraScale+ MPSoC Systems

ES (Easy Start)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

2 days

Oct 15, 2024

Info

Embedded Introduction Beginner Overview Zynq MPSoC Embedded Software C C++ Einführung Einstieg bit Bitstream Vivado Vitis AXI Cortex_A53 Cortex-R5 Processor BSP PMU Power IP-Integrator ACE easy start

Easy Start Embedded for Zynq UltraScale+ MPSoC Systems

ES (Easy Start)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

2 days

Dec 09, 2024

Info

Embedded Introduction Beginner Overview Zynq MPSoC Embedded Software C C++ Einführung Einstieg bit Bitstream Vivado Vitis AXI Cortex_A53 Cortex-R5 Processor BSP PMU Power IP-Integrator ACE easy start

Developing Multimedia Solutions with the VCU and GStreamer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

2 days

Jul 29, 2024

Info

SoM Vision Video streaming data application codec Kria Embedded Multimedia Gstreamer VCU Camera PetaLinux Linux Kernel

Developing Multimedia Solutions with the VCU and GStreamer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

2 days

Oct 17, 2024

Info

SoM Vision Video streaming data application codec Kria Embedded Multimedia Gstreamer VCU Camera PetaLinux Linux Kernel

Developing Multimedia Solutions with the VCU and GStreamer

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

2 days

Oct 17, 2024

Info

SoM Vision Video streaming data application codec Kria Embedded Multimedia Gstreamer VCU Camera PetaLinux Linux Kernel

Compact Zynq 7000 SoC for the Hardware Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

3 days

all year on request

Info

Embedded Architecture Vivado Vitis Zynq SoC Platform Hardware C AXI

Compact Zynq 7000 SoC for the Hardware Designer

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

3 days

all year on request

Info

Embedded Architecture Vivado Vitis Zynq SoC Platform Hardware C AXI

Compact Zynq UltraScale+ MPSoC for the Software Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

3 days

Aug 06, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Compact Zynq UltraScale+ MPSoC for the Software Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

3 days

Nov 18, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Compact Zynq UltraScale+ MPSoC for the Software Designer

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

3 days

Jul 29, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Compact Zynq UltraScale+ MPSoC for the Software Designer

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

3 days

Oct 28, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Compact Zynq UltraScale+ MPSoC for the Hardware Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

3 days

Aug 20, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE

Compact Zynq UltraScale+ MPSoC for the Hardware Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Munich

3 days

Nov 25, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE

Compact Zynq UltraScale+ MPSoC for the Hardware Designer

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

3 days

Oct 14, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE

Compact Versal Adaptive SoC for the Software Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

3 days

Aug 12, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC PMC

Compact Versal Adaptive SoC for the Software Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

3 days

Oct 28, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC PMC

Compact Versal Adaptive SoC for the Software Designer

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

3 days

Oct 28, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC PMC

Compact Versal Adaptive SoC for the Hardware Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Stuttgart

3 days

Oct 16, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC

Compact Versal Adaptive SoC for the Hardware Designer

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

3 days

Oct 16, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC

Compact Embedded Linux

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Stuttgart

3 days

Sep 02, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Yocto tool flow Zynq SoC

Compact Embedded Linux

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

3 days

Nov 05, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Yocto tool flow Zynq SoC

Compact Embedded Linux

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

3 days

Nov 05, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Yocto tool flow Zynq SoC

Advanced Zynq UltraScale+ MPSoC for the Hardware Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

3 days

Sep 25, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE

Advanced Zynq UltraScale+ MPSoC for the Hardware Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Stuttgart

3 days

Dec 16, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE

Advanced Zynq UltraScale+ MPSoC for the Hardware Designer

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

3 days

Dec 16, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE

Advanced Versal Adaptive SoC AI Engine

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

3 days

Sep 09, 2024

Info

Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP Acceleration & AI

Advanced Versal Adaptive SoC AI Engine

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Munich

3 days

Dec 04, 2024

Info

Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP Acceleration & AI

Advanced Versal Adaptive SoC AI Engine

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

3 days

Dec 04, 2024

Info

Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP Acceleration & AI

UVM Testbench Made Easy

WO (Workshop)

Programming Languages

Berlin

2 days

Jul 25, 2024

Info

FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions

UVM Testbench Made Easy

WO (Workshop)

Programming Languages

Freiburg

2 days

Oct 24, 2024

Info

FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions

UVM Testbench Made Easy

OL (Online Live)

Programming Languages

Online

2 days

Jul 25, 2024

Info

FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions

UVM Testbench Made Easy

OL (Online Live)

Programming Languages

Online

2 days

Oct 24, 2024

Info

FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions

SystemVerilog Advanced Verification for FPGA Design

WO (Workshop)

Programming Languages

Freiburg

3 days

Oct 21, 2024

Info

FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis

SystemVerilog Advanced Verification for FPGA Design

OL (Online Live)

Programming Languages

Online

3 days

Oct 21, 2024

Info

FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis

Professional VHDL

PW (Power Workshop)

Programming Languages

Frankfurt / Main

5 days

Oct 21, 2024

Info

FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis

Professional VHDL

PW (Power Workshop)

Programming Languages

Freiburg

5 days

Dec 02, 2024

Info

FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis

Professional VHDL

OL (Online Live)

Programming Languages

Online

5 days

Oct 21, 2024

Info

FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis

Professional VHDL Testbenches and Verification with OSVVM

PW (Power Workshop)

Programming Languages

Freiburg

5 days

Sep 16, 2024

Info

FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI

Professional VHDL Testbenches and Verification with OSVVM

PW (Power Workshop)

Programming Languages

Stuttgart

5 days

Nov 18, 2024

Info

FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI

Professional VHDL Testbenches and Verification with OSVVM

OL (Online Live)

Programming Languages

Online

5 days

Nov 18, 2024

Info

FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI

Professional Python for Embedded

PW (Power Workshop)

Programming Languages

Frankfurt / Main

5 days

Sep 23, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Professional Python for Embedded

PW (Power Workshop)

Programming Languages

Berlin

5 days

Nov 25, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Professional Python for Embedded

OL (Online Live)

Programming Languages

Online

5 days

Nov 25, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Compact VHDL for Synthesis

WO (Workshop)

Programming Languages

Stuttgart

3 days

Sep 02, 2024

Info

FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado

Compact VHDL for Synthesis

WO (Workshop)

Programming Languages

Munich

3 days

Nov 04, 2024

Info

FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado

Compact VHDL for Synthesis

OL (Online Live)

Programming Languages

Online

3 days

Aug 12, 2024

Info

FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado

Compact VHDL for Synthesis

OL (Online Live)

Programming Languages

Online

3 days

Nov 25, 2024

Info

FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado

Compact VHDL for Simulation

WO (Workshop)

Programming Languages

Stuttgart

2 days

Sep 05, 2024

Info

FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation

Compact VHDL for Simulation

WO (Workshop)

Programming Languages

Munich

2 days

Nov 07, 2024

Info

FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation

Compact VHDL for Simulation

OL (Online Live)

Programming Languages

Online

2 days

Aug 15, 2024

Info

FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation

Compact VHDL for Simulation

OL (Online Live)

Programming Languages

Online

2 days

Nov 28, 2024

Info

FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation

Compact Python for Embedded

WO (Workshop)

Programming Languages

Frankfurt / Main

3 days

Sep 23, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Compact Python for Embedded

WO (Workshop)

Programming Languages

Berlin

3 days

Nov 25, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Compact Python for Embedded

OL (Online Live)

Programming Languages

Online

3 days

Nov 25, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Designing with Ethernet MAC Controllers

WO (Workshop)

Connectivity

Berlin

2 days

Sep 11, 2024

Info

Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP

Designing with Ethernet MAC Controllers

WO (Workshop)

Connectivity

Freiburg

2 days

Nov 21, 2024

Info

Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP

Designing with Ethernet MAC Controllers

OL (Online Live)

Connectivity

Online

2 days

Nov 13, 2024

Info

Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP

Compact Zynq UltraScale+ RFSoC

WO (Workshop)

Connectivity

Frankfurt / Main

3 days

Sep 16, 2024

Info

RFSoC ADC DAC RF UltraScale+ Data Converter

Compact Zynq UltraScale+ RFSoC

WO (Workshop)

Connectivity

Munich

3 days

Dec 09, 2024

Info

RFSoC ADC DAC RF UltraScale+ Data Converter

Compact Zynq UltraScale+ RFSoC

OL (Online Live)

Connectivity

Online

3 days

Dec 09, 2024

Info

RFSoC ADC DAC RF UltraScale+ Data Converter

Compact Versal Adaptive SoC: Power and Board Design

WO (Workshop)

Connectivity

3 days

all year on request

Info

Embedded ACAP board design integrity power Versal Cortex-A72 Cortex-R5 NoC DDR4 AXI XPE power design Power Supply PDM Signal Integrity Reflection Crosstalk IBIS

Compact Versal Adaptive SoC: Power and Board Design

OL (Online Live)

Connectivity

3 days

all year on request

Info

Embedded ACAP board design integrity power Versal Cortex-A72 Cortex-R5 NoC DDR4 AXI XPE power design Power Supply PDM Signal Integrity Reflection Crosstalk IBIS

Compact Versal Adaptive SoC: Connectivity

WO (Workshop)

Connectivity

Stuttgart

3 days

Aug 12, 2024

Info

Versal High-Speed Interfaces ACAP 10GE 100GE 400GE MAC PCS FEC transceiver PLL hard IP Aurora DDR4 memory interface VCK190 Gigabit Ethernet

Compact Versal Adaptive SoC: Connectivity

WO (Workshop)

Connectivity

Frankfurt / Main

3 days

Nov 04, 2024

Info

Versal High-Speed Interfaces ACAP 10GE 100GE 400GE MAC PCS FEC transceiver PLL hard IP Aurora DDR4 memory interface VCK190 Gigabit Ethernet

Compact Versal Adaptive SoC: Connectivity

OL (Online Live)

Connectivity

Online

3 days

Oct 07, 2024

Info

Versal High-Speed Interfaces ACAP 10GE 100GE 400GE MAC PCS FEC transceiver PLL hard IP Aurora DDR4 memory interface VCK190 Gigabit Ethernet

Compact UltraScale: Serial Transceivers

WO (Workshop)

Connectivity

Frankfurt / Main

3 days

Sep 23, 2024

Info

UltraScale Serial Transceiver GTX GTH GTY 8B/10B 64B/66B 64B/67B UltraScale+ gearbox PLL KCU105

Compact UltraScale: Serial Transceivers

OL (Online Live)

Connectivity

Online

3 days

Nov 18, 2024

Info

UltraScale Serial Transceiver GTX GTH GTY 8B/10B 64B/66B 64B/67B UltraScale+ gearbox PLL KCU105

Compact UltraScale: High-Speed Memory Interfacing

WO (Workshop)

Connectivity

3 days

all year on request

Info

7Series DDR3 memory Memory Controller PCB Design PCB Design Rules Debugging DDR3 UltraScale UltraScale+ DDR4 memory

Compact UltraScale: High-Speed Memory Interfacing

OL (Online Live)

Connectivity

3 days

all year on request

Info

7Series DDR3 memory Memory Controller PCB Design PCB Design Rules Debugging DDR3 UltraScale UltraScale+ DDR4 memory

Compact UltraScale: Board Design and Signal Integrity

WO (Workshop)

Connectivity

3 days

all year on request

Info

UltraScale Power Supply board design power integrity Signal Integrity Reflection Crosstalk HyperLynx IBIS AMI Models PCB Simulation High-Speed Interfaces Transceiver PCI Express DDR4 PCB Design UltraScale+ board design power design Power Supply XPE Signal Integrity Reflection Crosstalk IBIS

Compact UltraScale: Board Design and Signal Integrity

OL (Online Live)

Connectivity

3 days

all year on request

Info

UltraScale Power Supply board design power integrity Signal Integrity Reflection Crosstalk HyperLynx IBIS AMI Models PCB Simulation High-Speed Interfaces Transceiver PCI Express DDR4 PCB Design UltraScale+ board design power design Power Supply XPE Signal Integrity Reflection Crosstalk IBIS

AXI Interface Technology

WO (Workshop)

Connectivity

Berlin

2 days

Sep 09, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

WO (Workshop)

Connectivity

Munich

2 days

Nov 28, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

OL (Online Live)

Connectivity

Online

2 days

Aug 01, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

OL (Online Live)

Connectivity

Online

2 days

Dec 09, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

Compact UltraScale: Integrated PCI Express Systems

WO (Workshop)

Connectivity

Munich

3 days

Sep 02, 2024

Info

UltraScale PCI Express Integrated Block for PCI Express Gen3 PL PCIe UltraScale+ PCIe endpoint root port DMA KCU105

Compact UltraScale: Integrated PCI Express Systems

WO (Workshop)

Connectivity

Berlin

3 days

Dec 02, 2024

Info

UltraScale PCI Express Integrated Block for PCI Express Gen3 PL PCIe UltraScale+ PCIe endpoint root port DMA KCU105

Compact UltraScale: Integrated PCI Express Systems

OL (Online Live)

Connectivity

Online

3 days

Nov 11, 2024

Info

UltraScale PCI Express Integrated Block for PCI Express Gen3 PL PCIe UltraScale+ PCIe endpoint root port DMA KCU105

FPGA Designer (Long Term)

LT (Long Term Education)

Development
Tools & Methodology

Freiburg

8 dates of 2 days each

Sep 10, 2024

Info

Embedded Designer (Long Term)

LT (Long Term Education)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

8 dates of 2 days each

Oct 01, 2024

Info

Compact Vivado Design Suite Tool Flow

WO (Workshop)

Development
Tools & Methodology

Stuttgart

2 days

Sep 16, 2024

Info

Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode

Compact Vivado Design Suite Tool Flow

WO (Workshop)

Development
Tools & Methodology

Munich

2 days

Nov 04, 2024

Info

Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode

Compact Vivado Design Suite Tool Flow

OL (Online Live)

Development
Tools & Methodology

Online

2 days

Oct 07, 2024

Info

Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode

Compact Timing Constraints and Analysis

WO (Workshop)

Development
Tools & Methodology

Stuttgart

3 days

Sep 18, 2024

Info

Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction

Compact Timing Constraints and Analysis

WO (Workshop)

Development
Tools & Methodology

Munich

3 days

Nov 06, 2024

Info

Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction

Compact Timing Constraints and Analysis

OL (Online Live)

Development
Tools & Methodology

Online

3 days

Jul 24, 2024

Info

Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction

Compact Timing Constraints and Analysis

OL (Online Live)

Development
Tools & Methodology

Online

3 days

Oct 09, 2024

Info

Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction

FPGA Circuit Design Technique

SE (Seminar)

Development
Tools & Methodology

Freiburg

1 day

Sep 25, 2024

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung IP Core

Professional Vivado

PW (Power Workshop)

Development
Tools & Methodology

Freiburg

5 days

Oct 07, 2024

Info

Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary

Professional Vivado

PW (Power Workshop)

Development
Tools & Methodology

Frankfurt / Main

5 days

Dec 09, 2024

Info

Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary

Professional Vivado

OL (Online Live)

Development
Tools & Methodology

Online

5 days

Oct 07, 2024

Info

Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary

Professional Vitis

PW (Power Workshop)

Development
Tools & Methodology

Freiburg

5 days

Aug 05, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT

Professional Vitis

PW (Power Workshop)

Development
Tools & Methodology

Berlin

5 days

Nov 04, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT

Professional Vitis

OL (Online Live)

Development
Tools & Methodology

Online

5 days

Nov 04, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT

Professional FPGA Circuit Design Technique

PW (Power Workshop)

Development
Tools & Methodology

Freiburg

5 days

Nov 04, 2024

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+

Professional FPGA Circuit Design Technique

OL (Online Live)

Development
Tools & Methodology

Online

5 days

Nov 04, 2024

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+

Git for EDA Tool Flows

WO (Workshop)

Development
Tools & Methodology

Munich

3 days

Sep 09, 2024

Info

Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging

Git for EDA Tool Flows

WO (Workshop)

Development
Tools & Methodology

Freiburg

3 days

Dec 16, 2024

Info

Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging

Git for EDA Tool Flows

OL (Online Live)

Development
Tools & Methodology

Online

3 days

Nov 11, 2024

Info

Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging

FPGA Power Optimization

WO (Workshop)

Development
Tools & Methodology

2 days

all year on request

Info

FPGA Power Vivado Kintex XCE clocking

FPGA Power Optimization

OL (Online Live)

Development
Tools & Methodology

2 days

all year on request

Info

FPGA Power Vivado Kintex XCE clocking

Easy Start FPGA Vivado

ES (Easy Start)

Development
Tools & Methodology

Freiburg

2 days

Aug 08, 2024

Info

FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start

Easy Start FPGA Vivado

ES (Easy Start)

Development
Tools & Methodology

Frankfurt / Main

2 days

Nov 14, 2024

Info

FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start

Easy Start FPGA Vivado

OL (Online Live)

Development
Tools & Methodology

Online

2 days

Jul 29, 2024

Info

FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start

Easy Start FPGA Vivado

OL (Online Live)

Development
Tools & Methodology

Online

2 days

Dec 04, 2024

Info

FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start

Dynamic Function eXchange (DFX)

WO (Workshop)

Development
Tools & Methodology

Freiburg

2 days

Oct 01, 2024

Info

FPGA DFX Vivado partial configuration functions Black Box Floorplaning

Dynamic Function eXchange (DFX)

OL (Online Live)

Development
Tools & Methodology

Online

2 days

Oct 01, 2024

Info

FPGA DFX Vivado partial configuration functions Black Box Floorplaning

Designing with the Xilinx Analog Mixed Signal Solution

WO (Workshop)

Development
Tools & Methodology

2 days

all year on request

Info

FPGA AMS Vivado XADC DAC

Designing with the Xilinx Analog Mixed Signal Solution

OL (Online Live)

Development
Tools & Methodology

2 days

all year on request

Info

FPGA AMS Vivado XADC DAC

Debugging Techniques Using the Vivado Logic Analyzer

WO (Workshop)

Development
Tools & Methodology

Stuttgart

2 days

Sep 12, 2024

Info

Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation

Debugging Techniques Using the Vivado Logic Analyzer

WO (Workshop)

Development
Tools & Methodology

Frankfurt / Main

2 days

Dec 02, 2024

Info

Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation

Debugging Techniques Using the Vivado Logic Analyzer

OL (Online Live)

Development
Tools & Methodology

Online

2 days

Dec 02, 2024

Info

Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation

Continuous Integration for EDA Tools

PW (Power Workshop)

Development
Tools & Methodology

Berlin

5 days

Oct 07, 2024

Info

FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL

Continuous Integration for EDA Tools

OL (Online Live)

Development
Tools & Methodology

Online

5 days

Oct 14, 2024

Info

FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL

Compact Vitis for the Software Designer

WO (Workshop)

Development
Tools & Methodology

Berlin

3 days

Sep 17, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging

Compact Vitis for the Software Designer

WO (Workshop)

Development
Tools & Methodology

Munich

3 days

Dec 16, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging

Compact Vitis for the Software Designer

OL (Online Live)

Development
Tools & Methodology

Online

3 days

Dec 16, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging

Compact Vitis for Acceleration

WO (Workshop)

Development
Tools & Methodology

Freiburg

3 days

Aug 12, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging

Compact Vitis for Acceleration

WO (Workshop)

Development
Tools & Methodology

Frankfurt / Main

3 days

Nov 20, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging

Compact Vitis for Acceleration

OL (Online Live)

Development
Tools & Methodology

Online

3 days

Nov 20, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging

Compact Vitis AI

WO (Workshop)

Development
Tools & Methodology

Stuttgart

3 days

Sep 23, 2024

Info

Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software

Compact Vitis AI

WO (Workshop)

Development
Tools & Methodology

Berlin

3 days

Nov 04, 2024

Info

Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software

Compact Vitis AI

OL (Online Live)

Development
Tools & Methodology

Online

3 days

Nov 04, 2024

Info

Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software

Compact FPGA Circuit Design Technique

WO (Workshop)

Development
Tools & Methodology

Stuttgart

3 days

Aug 05, 2024

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+

Compact FPGA Circuit Design Technique

WO (Workshop)

Development
Tools & Methodology

Berlin

3 days

Oct 09, 2024

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+

Compact FPGA Circuit Design Technique

OL (Online Live)

Development
Tools & Methodology

Online

3 days

Sep 16, 2026

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+

Compact FPGA Circuit Design Technique

OL (Online Live)

Development
Tools & Methodology

Online

3 days

Dec 09, 2024

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+

Compact Vitis HLS

WO (Workshop)

DSP & Image Processing

Freiburg

3 days

Aug 27, 2024

Info

Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface

Compact Vitis HLS

WO (Workshop)

DSP & Image Processing

Stuttgart

3 days

Nov 27, 2024

Info

Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface

Compact Vitis HLS

OL (Online Live)

DSP & Image Processing

Online

3 days

Jul 29, 2024

Info

Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface

Compact Vitis HLS

OL (Online Live)

DSP & Image Processing

Online

3 days

Oct 21, 2024

Info

Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface

Professional DSP Design Using Vitis Model Composer

PW (Power Workshop)

DSP & Image Processing

Freiburg

5 days

Sep 02, 2024

Info

DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox

Professional DSP Design Using Vitis Model Composer

PW (Power Workshop)

DSP & Image Processing

Berlin

5 days

Dec 16, 2024

Info

DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox

Professional DSP Design Using Vitis Model Composer

OL (Online Live)

DSP & Image Processing

Online

5 days

Dec 16, 2024

Info

DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox

Compact DSP Design for Versal Using Vitis Model Composer

WO (Workshop)

DSP & Image Processing

3 days

all year on request

Info

DSP Mathworks Matlab Tool Flow FPGA

Compact DSP Design for Versal Using Vitis Model Composer

OL (Online Live)

DSP & Image Processing

3 days

all year on request

Info

DSP Mathworks Matlab Tool Flow FPGA

Compact DSP Design for FPGAs Using Vitis Model Composer

WO (Workshop)

DSP & Image Processing

Freiburg

3 days

Sep 02, 2024

Info

DSP Mathworks Matlab Tool Flow FPGA

Compact DSP Design for FPGAs Using Vitis Model Composer

WO (Workshop)

DSP & Image Processing

Berlin

3 days

Dec 16, 2024

Info

DSP Mathworks Matlab Tool Flow FPGA

Compact DSP Design for FPGAs Using Vitis Model Composer

OL (Online Live)

DSP & Image Processing

Online

3 days

Dec 16, 2024

Info

DSP Mathworks Matlab Tool Flow FPGA

Zynq 7000 SoC for the System Architect

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

2 days

all year on request

Info

Embedded Architecture Vivado Vitis Zynq SoC Peripherals Memory

Zynq 7000 SoC for the System Architect

OL (Online Live)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

2 days

all year on request

Info

Embedded Architecture Vivado Vitis Zynq SoC Peripherals Memory

Zynq UltraScale+ MPSoC for the System Architect

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Freiburg

2 days

Sep 12, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE

Zynq UltraScale+ MPSoC for the System Architect

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Munich

2 days

Dec 19, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE

Zynq UltraScale+ MPSoC for the System Architect

OL (Online Live)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Online

2 days

Nov 20, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE

Versal Adaptive SoC for the System Architect

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Stuttgart

2 days

Aug 01, 2024

Info

Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI

Versal Adaptive SoC for the System Architect

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Munich

2 days

Nov 18, 2024

Info

Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI

Versal Adaptive SoC for the System Architect

OL (Online Live)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Online

2 days

Dec 11, 2024

Info

Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI

Professional FPGA

PW (Power Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Munich

5 days

Oct 21, 2024

Info

FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC

Professional FPGA

OL (Online Live)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Online

5 days

Oct 21, 2024

Info

FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC

Essentials of Microprocessors

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

1 day

all year on request

Info

Embedded Microcontroller Processor Compiler Cache Linker Debugger Vitis

Essentials of Microprocessors

OL (Online Live)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

1 day

all year on request

Info

Embedded Microcontroller Processor Compiler Cache Linker Debugger Vitis

Compact UltraScale/UltraScale+

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Frankfurt / Main

2 days

Sep 26, 2024

Info

FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO

Compact UltraScale/UltraScale+

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Stuttgart

2 days

Nov 21, 2024

Info

FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO

Compact UltraScale/UltraScale+

OL (Online Live)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Online

2 days

Oct 28, 2024

Info

FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO

Compact FPGA 7 Series

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

2 days

on request all year tbd

Info

FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP 7 series IO

Compact FPGA 7 Series

OL (Online Live)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

2 days

all year on request

Info

FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP 7 series IO

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TRAINING and CONSULTING ON THE JOB

Apply Your Learning Successfully on Your Current Project.

PLC2 unique »training on the job« provides you with onsite training during the development of your projects. In addition to the theoretical training by one of our experienced speakers, your current tasks and solutions are worked out at the same time resulting into a reduced development time.

Unexpected problems during the midst of a development are every engineer nightmare. We at PLC2 are here to help and consult you onsite to work out together a solution to your problems and help you achieve your deadlines.

Contact us below for further Information.

Contact us

What Our Customers Are Saying

»PLC2 has consistently demonstrated top-notch expertise in the realm of FPGA training and design reviews. Their team’s dedication and proficiency have made them our primary choice. We couldn’t be happier with the outcomes and insights they’ve provided.«

Arthur Bebernik

R&D Senior Engineer Hardware

ABB

»We at SCIENION, a global leader in Precision Cell Dispensing are continuously improving our products to include leading-edge technologies. With PLC2, we found a partner to reach our goals. PLC2 has a highly skilled staff in FPGA/SoC-related competencies and helped us complete our project successfully on time. PLC2 will definitely be our partner for the next technical challenges.«

Tarik Salt

Electronics Engineer

SCIENION GmbH

»As a recent graduate, I learned at PLC2 not only the basics about FPGAs and VHDL, but also the proper use of Vivado. The trainings have sustainably improved my work and I still benefit from them today. Due to the wide knowledge, PLC2 is also the right contact for detailed technical questions about Xilinx products.«

Konstantin Wagner

Software Engineer Power Electronics

Maschinenfabrik Reinhausen GmbH

»PLC2 is a competent partner in all areas related to FPGA design. The workshops and seminars offered cover the entire spectrum of the FPGA world and they are also available at any time for specific project-related support.«

Thomas Donner

Management Center Elektronik (MCE)

Stöber Antriebstechnik GmbH & Co. KG

»We did our recent FPGA project in collaboration with PLC2. Our team was very satisfied with their expertise in FPGA design, their availability and responsiveness throughout the project which finally made the project a success. We highly recommend them to anyone looking for reliable and knowledgeable service providers. Thank you, PLC2, for your contribution to our project!«

Dr. Lothar Springob

System Integration Manager

Bonfiglioli Vectron GmbH

»We have been customer of PLC2 for many years and have enjoyed the friendly and competent way of working with them. PLC2 is therefore still our first contact when we need training on special FPGA topics. Frequently, we have also enjoyed in-house visits from PLC2, where we have received training, consulting and design reviews tailored to our needs. Also, the annual FPGA conference is a very good opportunity to get an insight into current FPGA trends and to exchange experiences with other FPGA developers.«

Stefan Eiermann

Electronics Hardware Principal Technical Expert

Schneider Electric Automation GmbH

How can we help?

Contact

FAQ

01. Can you help me with reserving the room?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

02. What times in the day do courses start and end?

Our face-to-face courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours. For online courses, the start is also at 9 a.m. (CET/CEST), but they end at 2:30 p.m.. The total course time per day is 4 and a half hours plus breaks.

03. Are course materials provided?

All participants of paid courses will receive English training materials in electronic or paper form.

04. Will I receive a course certificate?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

05. Can I pay with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

06. What are the options for payment?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

07. What is the deadline for payment?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

08. What are the options for cancelling?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

09. When will I receive a firm commitment as to whether the course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

10. How many participants are required for a course to be given/what is the minimum number of participants?

We generally offer courses for 5 or more people. That means that if you would like to book a course at your premises, you need 5 people to register or need to pay the amount for 5 participants, even if fewer people attend.

11. Can I book a course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

12. What language is the course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.