Technical Training in a Renowned Training Center

PLC2 Training Courses Around FPGAs, SoCs, MPSoCs, Programming Languages, and More

We at PLC2 provide first-class expert training classes addressing today’s engineering challenges.

Advanced technologies, tools and methodologies for FPGAs and embedded systems are developing at a lighting pace. How do you deal with all these new development opportunities created by state of the art technologies?

PLC2 is the Expert Authorized Training Provider partner for AMD. We provide training around embedded solutions with core competencies in FPGA technologies. We have trained 1000s of engineers across the world thanks to the inhouse knowledge we developed over the last 30 years.

Choose the training format that suits you, a 2-day course, an intensive long-term training, or on the job coaching. PLC2 is your partner for your next challenge.

PLC2 Training Calendar 2025
Bring your colleagues to your next training. Up from the second booking of the same training course you will save 30 %.*

Training Calendar

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The PLC2 Training
Offering Is Divided
into the Following
6 Categories:

AMD Architecture

In today’s competitive world of electronic engineering the difference is made at the system architectural level. Making the right choices at the start of your design makes the difference between mediocre versus excellent results.

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Development
Tools & Methodology

The HDL based development method simplifies the development cycle, but this requires the developer to have good knowledge of digital circuit design.

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Programming Languages

Familiarize yourself with the latest design methods to get the most out of your chosen technology. Learn the fundamentals and become an expert in HDL languages such as VHDL or System Verilog.

Learn more

PLC2 training category on tools and methodology

Embedded Development

Are you a beginner in the embedded world or a very experienced embedded developer, we at PLC2 tailor our embedded classes to your level. Our workshops include everything you need to know on how to develop embedded solutions with AMD’s wide range of SoCs.

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DSP & Image Processing

With their inherent flexibility, AMD FPGAs and SoCs are ideal for high-performance or multi-channel digital signal processing (DSP) applications that can take advantage of hardware parallelism.

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FPGA Connectivity & Protocols

How do you keep up with the edge network emerging applications that are redefining hardware requirements for electronic designers? Are you designing the next generation AI for IoT, embedded vision, hardware security, 5G communication or industrial/automotive automation for your company?

Learn more

Training Formats

Online Live

Online course
In-depth exercises in real-time
Remote access on utilized software and hardware

EXPLORE

Webinar

Good overview of a topic
Technical focus
Online

EXPLORE

Seminar

1-day technical deep dive
Free of charge
For developers, department heads, and managers

EXPLORE

Easy Start

Perfect for beginners and project managers
With a focus on practical exercises

EXPLORE

Workshop

Compact 1- to 3-day workshop
Ideal for developers
Theory and practice

EXPLORE

Power Workshop

5-day power workshop
Very extensive further training
Practice-oriented on PC and evaluation board
Detailed treatment of technical topics

EXPLORE

Long Term Education

3 months training
For engineers and technicians
Including comprehensive training material

EXPLORE

All Trainings

Course	Format	Category	Location	Duration	Date
System Design Insights: Mapping Designs on Heterogeneous Adaptive SoC Targets	WE (Webinar)	Embedded Development	Online	11-12 am CEST	Jul 31, 2025	Info
Accelerate Your DSP Compute Loads with Versal AI Engines	WE (Webinar)	DSP & Image Processing	Online	11-12 am CEST	Jun 26, 2025	Info
Think Before You Save! – Vivado Design Flow	WE (Webinar)	Development Tools & Methodology	Online	1 hour	on request	Info Vivado Implementation, Constraining, Vivado Design run, Hardware design flow, UltraFast UFD Ultrafast Design Methodology
Embedded System Basics for AMD	WE (Webinar)	Embedded Development	Online	1 hour	on demand	Info Adaptive SoC, Zynq, Embedded, software programming, hardware programming,
System Debugging Using Cross-Triggering Features	WE (Webinar)	Embedded Development	Online	1 hour	on demand	Info vitis vivado debugging cross-triggering
Using the Adaptive SoC TRDs to Test Custom Image Recognition Tasks	WE (Webinar)	Embedded Development	Online	1 hour	on demand	Info AMD Adaptive SoC TRDs Custom Image Recognition vision
Deep Neural Networks on Edge Devices with Vitis AI	WE (Webinar)	Embedded Development	Online	1 hour	on demand	Info adaptive SoC FPGA AMD vision CNN neural networks Vitis AI toolchain DPU
All about Memories in Adaptive SoCs	WE (Webinar)	Embedded Development	Online	1 hour	on demand	Info adaptive SoC memory programming FPGA AMD webinar, Memories, Memory, UltraRAM, BlockRAM, Memory Access, Adaptive SoC
VHDL Circuit Simulation Part 2: Stimulus Generation and Behavior Verification	WE (Webinar)	Programming Languages	Online	1 hour	on demand	Info VHDL circuit simulation simulations FPGA AMD webinar
VHDL Circuit Simulation Part 1: Behavior Modeling, Timing, and File I/O	WE (Webinar)	Programming Languages	Online	1 hour	on demand	Info VHDL circuit simulation simulations FPGA AMD webinar
VHDL Circuit Design Part 2: Advanced Concepts and Behavioral Modeling	WE (Webinar)	Programming Languages	Online	1 hour	on demand	Info VHDL circuit design designs application applications behavioral modeling AMD webinar
VHDL Circuit Design Part 1: Fundamentals and Methodologies	WE (Webinar)	Programming Languages	Online	1 hour	on demand	Info VHDL circuit design designs application applications AMD webinar HDL hardware design
FPGA Timing Constraints: A Comprehensive Overview	WE (Webinar)	Development Tools & Methodology	Online	1 hour	on demand	Info FPGA timing constraints AMD Vivado AMD FPGA design flow virtual clocks webinar
Mastering Clock Domain Crossing: Strategies for Synchronization and Stability	WE (Webinar)	AMD Architecture	Online	1 hour	on demand	Info clock domain crossing AMDF FPGA FPGAs metastability synchronizers MTBF signal synchronization AMD webinar
FPGA Circuit Design Part 2: Interfaces and Best Practices	WE (Webinar)	AMD Architecture	Online	1 hour	on demand	Info FPGA Circuit Design designs synchronous asynchronous design techniques technique designing state machines machine AMD webinar
FPGA Circuit Design Part 1: Synchronous and Asynchronous Design Techniques	WE (Webinar)	AMD Architecture	Online	1 hour	on demand	Info FPGA Circuit Design designs synchronous asynchronous design techniques technique, designing state machines machine AMD
Developing Demanding Applications with Versal Adaptive SoCs	OL (Online Live)	AMD Architecture	Online	1 day	the whole year tbd	Info Seminar Versal Adaptive SoC Vitis Unififed Development Platform design integration
Microservice Applications on Versal and Other Adaptive SoCs	WE (Webinar)	Embedded Development	Online	1 hour	on demand	Info
Fast Track Evaluation of ML Models on Versal Adaptive SoC	WE (Webinar)	DSP & Image Processing	Online	1 hour	on demand	Info
Vitis Model Composer for Kria SoM: Block Diagram Based Accelerator Design	WE (Webinar)	Embedded Development	Online	1 hour	on demand	Info
NEW \| Yocto Embedded Linux Development	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	2 days	Sep 25, 2025	Info Yocto, Linux, PetaLinux, Open-Source, Zynq, Kernel, rootfs, device driver
NEW \| Yocto Embedded Linux Development	WO (Workshop)	Development Tools & Methodology	Freiburg	2 days	Nov 20, 2025	Info Yocto, Linux, PetaLinux, Open-Source, Zynq, Kernel, rootfs, device driver
Scripting the AMD Hardware Design Flow Using Vivado	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	Sep 22, 2025	Info
Scripting the AMD Hardware Design Flow Using Vivado	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	Nov 12, 2025	Info
Scripting the AMD Hardware Design Flow Using Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 22, 2025	Info
Scripting the AMD Hardware Design Flow Using Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 12, 2025	Info
Circuit Synthesis with VHDL	SE (Seminar)	Programming Languages	Stuttgart	1 day	Oct 01, 2025	Info FPGA HDL VHDL HDL Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream
Circuit Simulation with VHDL	SE (Seminar)	Programming Languages	Frankfurt / Main	1 day	Nov 12, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation
Compact SystemVerilog for Synthesis	WO (Workshop)	Programming Languages	Freiburg	3 days	Jul 28, 2025	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact SystemVerilog for Synthesis	WO (Workshop)	Programming Languages	Munich	3 days	Oct 29, 2025	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact SystemVerilog for Synthesis \| Online	OL (Online Live)	Programming Languages	Online	3 days	Jul 28, 2025	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact SystemVerilog for Synthesis \| Online	OL (Online Live)	Programming Languages	Online	3 days	Oct 29, 2025	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Easy Start ML Application Design Flow	ES (Easy Start)	Embedded Development	Frankfurt / Main	2 days	Jul 08, 2025	Info Easy Start ML Application Design Flow Machine Learning Vitis AI AMD adaptive SoCs AMD adaptive SoC Deep Learning Processing Unit DPU PyTorch TensorFlow
Easy Start ML Application Design Flow	ES (Easy Start)	Embedded Development	Stuttgart	2 days	Oct 15, 2025	Info Easy Start ML Application Design Flow Machine Learning Vitis AI AMD adaptive SoCs AMD adaptive SoC Deep Learning Processing Unit DPU PyTorch TensorFlow
Easy Start ML Application Design Flow	ES (Easy Start)	Embedded Development	Munich	2 days	Dec 01, 2025	Info Easy Start ML Application Design Flow Machine Learning Vitis AI AMD adaptive SoCs AMD adaptive SoC Deep Learning Processing Unit DPU PyTorch TensorFlow
Easy Start Embedded Flow	ES (Easy Start)	Embedded Development	Berlin	2 days	Sep 09, 2025	Info Easy Start Embedded AMD programmable platforms adaptive SoCs adaptive SoC FPGA FPGAs processor core Vivado Vitis c c++ c/c++ AMD FPGAs and adaptive SoCs technology programming languages VHDL AXI hardware design
Easy Start Embedded Flow	ES (Easy Start)	Embedded Development	Stuttgart	2 days	Nov 27, 2025	Info Easy Start Embedded AMD programmable platforms adaptive SoCs adaptive SoC FPGA FPGAs processor core Vivado Vitis c c++ c/c++ AMD FPGAs and adaptive SoCs technology programming languages VHDL AXI hardware design
Advanced VHDL	WO (Workshop)	Programming Languages	Frankfurt / Main	3 days	Jul 21, 2025	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL	WO (Workshop)	Programming Languages	Freiburg	3 days	Oct 29, 2025	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL	WO (Workshop)	Programming Languages	Munich	3 days	Dec 15, 2025	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL \| Online	OL (Online Live)	Programming Languages	Online	3 days	Jul 21, 2025	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL \| Online	OL (Online Live)	Programming Languages	Online	3 days	Oct 29, 2025	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL \| Online	OL (Online Live)	Programming Languages	Online	3 days	Dec 15, 2025	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Compact MicroBlaze System Design	OL (Online Live)	Embedded Development	Online	3 days	all year on request	Info Embedded MicroBlaze System Design Systems FPGA hardware software AMD tool tools custom peripheral application debugging integration microprocessor microprocessors Vivado Vitis
Compact MicroBlaze System Design \| Online	WO (Workshop)	Embedded Development		3 days	all year on request	Info Embedded MicroBlaze System Design Systems FPGA hardware software AMD tool tools custom peripheral application debugging integration microprocessor microprocessors Vivado Vitis
Compact VHDL Testbenches and Verification with OSVVM	WO (Workshop)	Programming Languages	Berlin	3 days	Aug 05, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Compact VHDL Testbenches and Verification with OSVVM	WO (Workshop)	Programming Languages	Munich	3 days	Oct 06, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Compact VHDL Testbenches and Verification with OSVVM \| Online	OL (Online Live)	Programming Languages	Online	3 days	Aug 05, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Compact VHDL Testbenches and Verification with OSVVM \| Online	OL (Online Live)	Programming Languages	Online	3 days	Oct 06, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Advanced Vivado	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Jul 21, 2025	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	Oct 29, 2025	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Jul 21, 2025	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Oct 29, 2025	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Compact Versal Adaptive SoC: PCI Express Systems	WO (Workshop)	FPGA Connectivity & Protocols	Stuttgart	2 days	Oct 15, 2025	Info Versal PCI Express Integrated Block for PCI Express Gen4 PL PCIe CPM PCIe High-Speed Interfaces Transceiver DDR4 PCB Design PCB Simulation ACAP PCIe endpoint root port DMA VCK190
Compact Versal Adaptive SoC: PCI Express Systems \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	2 days	Oct 15, 2025	Info Versal PCI Express Integrated Block for PCI Express Gen4 PL PCIe CPM PCIe High-Speed Interfaces Transceiver DDR4 PCB Design PCB Simulation ACAP PCIe endpoint root port DMA VCK190
Kria for the Software Developer	SE (Seminar)	Embedded Development		1 day	all year on request	Info SoM Acceleration Vitis tool flow Zynq MPSoC Software C
Professional Versal Adaptive SoC	PW (Power Workshop)	Embedded Development	Frankfurt / Main	5 days	Sep 15, 2025	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI
Professional Versal Adaptive SoC	PW (Power Workshop)	Embedded Development	Stuttgart	5 days	Nov 10, 2025	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI
Professional Versal Adaptive SoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	Sep 15, 2025	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI
Professional Versal Adaptive SoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	Nov 10, 2025	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI
Compact Zynq 7000 SoC for the Software Designer	WO (Workshop)	Embedded Development		3 days	all year on request	Info Embedded Architecture Vivado Vitis SoC Cortex-A9 Processor Cache PetaLinux Linux PS AXI
Compact Zynq 7000 SoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	all year on request	Info Embedded Architecture Vivado Vitis SoC Cortex-A9 Processor Cache PetaLinux Linux PS AXI
Professional Zynq 7000 SoC	PW (Power Workshop)	Embedded Development		5 days	all year on request	Info Embedded Architecture Vivado Vitis Zynq SoC Boot Software C C++ AXI Configuration System Integration Debugging AXI
Professional Zynq 7000 SoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	all year on request	Info Embedded Architecture Vivado Vitis Zynq SoC Boot Software C C++ AXI Configuration System Integration Debugging AXI
Professional Zynq UltraScale+ MPSoC	PW (Power Workshop)	Embedded Development	Freiburg	5 days	Sep 15, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Professional Zynq UltraScale+ MPSoC	PW (Power Workshop)	Embedded Development	Frankfurt / Main	5 days	Dec 08, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Professional Zynq UltraScale+ MPSoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	Sep 15, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Professional Zynq UltraScale+ MPSoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	Dec 08, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Expert Zynq 7000 SoC	PW (Power Workshop)	Embedded Development		5 days	all year on request	Info Embedded Architecture Vivado Vitis SoC Cortex-A9 Processor Cache PetaLinux IP-Integrator Linux PS AXI
Expert Zynq 7000 SoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	all year on request	Info Embedded Architecture Vivado Vitis SoC Cortex-A9 Processor Cache PetaLinux IP-Integrator Linux PS AXI
Expert Versal Adaptive SoC AI Engine	PW (Power Workshop)	Embedded Development	Freiburg	5 days	Jul 14, 2025	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP , Acceleration & AI
Expert Versal Adaptive SoC AI Engine	PW (Power Workshop)	Embedded Development	Frankfurt / Main	5 days	Oct 06, 2025	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP , Acceleration & AI
Expert Versal Adaptive SoC AI Engine \| Online	OL (Online Live)	Embedded Development	Online	5 days	Jul 14, 2025	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP , Acceleration & AI
Expert Versal Adaptive SoC AI Engine \| Online	OL (Online Live)	Embedded Development	Online	5 days	Oct 06, 2025	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP , Acceleration & AI
Embedded Linux Driver Development	WO (Workshop)	Embedded Development		3 days	all year on request	Info Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Driver Character Yocto tool flow Zynq
Embedded Linux Driver Development \| Online	OL (Online Live)	Embedded Development	Online	3 days	all year on request	Info Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Driver Character Yocto tool flow Zynq
Embedded Design with PetaLinux Tools	WO (Workshop)	Embedded Development	Berlin	2 days	Sep 11, 2025	Info Embedded Linux PetaLinux build rootfs kernel driver layer DeviceTree Device-Tree Boot
Embedded Design with PetaLinux Tools	WO (Workshop)	Embedded Development	Munich	2 days	Nov 25, 2025	Info Embedded Linux PetaLinux build rootfs kernel driver layer DeviceTree Device-Tree Boot
Embedded Design with PetaLinux Tools \| Online	OL (Online Live)	Embedded Development	Online	2 days	Sep 11, 2025	Info Embedded Linux PetaLinux build rootfs kernel driver layer DeviceTree Device-Tree Boot
Embedded Design with PetaLinux Tools \| Online	OL (Online Live)	Embedded Development	Online	2 days	Nov 25, 2025	Info Embedded Linux PetaLinux build rootfs kernel driver layer DeviceTree Device-Tree Boot
Easy Start Kria for Vision Development	ES (Easy Start)	Embedded Development	Freiburg	2 days	Sep 25, 2025	Info SOM Vision Vivado Vitis AI Kria Image Processing Vision Kernel Rootfs DeviceTree Device-Tree Embedded mulitmedia camera PetaLinux Linux easy start
Easy Start Kria for Vision Development	ES (Easy Start)	Embedded Development	Berlin	2 days	Nov 10, 2025	Info SOM Vision Vivado Vitis AI Kria Image Processing Vision Kernel Rootfs DeviceTree Device-Tree Embedded mulitmedia camera PetaLinux Linux easy start
Easy Start Embedded PetaLinux	ES (Easy Start)	Embedded Development		2 days	all year on request	Info Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Rootfs Zynq easy start
Easy Start Embedded for Zynq-7000 SoC Systems	ES (Easy Start)	Embedded Development		2 days	all year on request	Info Embedded Introduction Beginner Overview Zynq SoC Embedded Software C C++ Einführung Einstieg bit Bitstream Vivado Vitis AXI Cortex-A9 Processor DSP PS Software Development easy start
Easy Start Embedded for Zynq UltraScale+ MPSoC Systems	ES (Easy Start)	Embedded Development	Frankfurt / Main	2 days	Jul 30, 2025	Info Embedded Introduction Beginner Overview Zynq MPSoC Embedded Software C C++ Einführung Einstieg bit Bitstream Vivado Vitis AXI Cortex_A53 Cortex-R5 Processor BSP PMU Power IP-Integrator ACE easy start
Easy Start Embedded for Zynq UltraScale+ MPSoC Systems	ES (Easy Start)	Embedded Development	Berlin	2 days	Oct 07, 2025	Info Embedded Introduction Beginner Overview Zynq MPSoC Embedded Software C C++ Einführung Einstieg bit Bitstream Vivado Vitis AXI Cortex_A53 Cortex-R5 Processor BSP PMU Power IP-Integrator ACE easy start
Easy Start Embedded for Zynq UltraScale+ MPSoC Systems	ES (Easy Start)	Embedded Development	Freiburg	2 days	Dec 08, 2025	Info Embedded Introduction Beginner Overview Zynq MPSoC Embedded Software C C++ Einführung Einstieg bit Bitstream Vivado Vitis AXI Cortex_A53 Cortex-R5 Processor BSP PMU Power IP-Integrator ACE easy start
Developing Multimedia Solutions with the VCU and GStreamer	WO (Workshop)	Embedded Development	Frankfurt / Main	2 days	Jul 28, 2025	Info SoM Vision Video streaming data application codec Kria Embedded Multimedia Gstreamer VCU Camera PetaLinux Linux Kernel
Developing Multimedia Solutions with the VCU and GStreamer	WO (Workshop)	Embedded Development	Berlin	2 days	Oct 09, 2025	Info SoM Vision Video streaming data application codec Kria Embedded Multimedia Gstreamer VCU Camera PetaLinux Linux Kernel
Developing Multimedia Solutions with the VCU and GStreamer \| Online	OL (Online Live)	Embedded Development	Online	2 days	Jul 28, 2025	Info SoM Vision Video streaming data application codec Kria Embedded Multimedia Gstreamer VCU Camera PetaLinux Linux Kernel
Developing Multimedia Solutions with the VCU and GStreamer \| Online	OL (Online Live)	Embedded Development	Online	2 days	Oct 09, 2025	Info SoM Vision Video streaming data application codec Kria Embedded Multimedia Gstreamer VCU Camera PetaLinux Linux Kernel
Compact Zynq 7000 SoC for the Hardware Designer	WO (Workshop)	Embedded Development		3 days	all year on request	Info Embedded Architecture Vivado Vitis Zynq SoC Platform Hardware C AXI
Compact Zynq 7000 SoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	all year on request	Info Embedded Architecture Vivado Vitis Zynq SoC Platform Hardware C AXI
NEW \| Advanced Zynq UltraScale+ MPSoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Sep 22, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
NEW \| Advanced Zynq UltraScale+ MPSoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Dec 03, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
NEW \| Advanced Zynq UltraScale+ MPSoC for the Software Designer	WO (Workshop)	Embedded Development	Stuttgart	3 days	Sep 22, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
NEW \| Advanced Zynq UltraScale+ MPSoC for the Software Designer	WO (Workshop)	Embedded Development	Munich	3 days	Dec 03, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Compact Zynq UltraScale+ MPSoC for the Software Designer	WO (Workshop)	Embedded Development	Berlin	3 days	Aug 05, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Compact Zynq UltraScale+ MPSoC for the Software Designer	WO (Workshop)	Embedded Development	Freiburg	3 days	Nov 17, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Compact Zynq UltraScale+ MPSoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Aug 05, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Compact Zynq UltraScale+ MPSoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Nov 17, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Compact Zynq UltraScale+ MPSoC for the Hardware Designer	WO (Workshop)	Embedded Development	Berlin	3 days	Aug 19, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE
Compact Zynq UltraScale+ MPSoC for the Hardware Designer	WO (Workshop)	Embedded Development	Munich	3 days	Nov 03, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE
Compact Zynq UltraScale+ MPSoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Aug 19, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE
Compact Zynq UltraScale+ MPSoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Nov 03, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE
Compact Versal Adaptive SoC for the Software Designer	WO (Workshop)	Embedded Development	Freiburg	3 days	Aug 25, 2025	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC PMC
Compact Versal Adaptive SoC for the Software Designer	WO (Workshop)	Embedded Development	Berlin	3 days	Oct 07, 2025	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC PMC
Compact Versal Adaptive SoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Aug 25, 2025	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC PMC
Compact Versal Adaptive SoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Oct 07, 2025	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC PMC
Compact Versal Adaptive SoC for the Hardware Designer	WO (Workshop)	Embedded Development	Munich	3 days	Jul 21, 2025	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC
Compact Versal Adaptive SoC for the Hardware Designer	WO (Workshop)	Embedded Development	Stuttgart	3 days	Oct 13, 2025	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC
Compact Versal Adaptive SoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Jul 21, 2025	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC
Compact Versal Adaptive SoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Oct 13, 2025	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC
Compact Embedded Linux	WO (Workshop)	Embedded Development		3 days	all year on request	Info Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Yocto tool flow Zynq SoC
Compact Embedded Linux \| Online	OL (Online Live)	Embedded Development	Online	3 days	all year on request	Info Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Yocto tool flow Zynq SoC
Advanced Zynq UltraScale+ MPSoC for the Hardware Designer	WO (Workshop)	Embedded Development		3 days	all year on request	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE
Advanced Zynq UltraScale+ MPSoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	all year on request	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE
Advanced Versal Adaptive SoC AI Engine	WO (Workshop)	Embedded Development	Freiburg	3 days	Sep 22, 2025	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP Acceleration & AI
Advanced Versal Adaptive SoC AI Engine	WO (Workshop)	Embedded Development	Munich	3 days	Dec 15, 2025	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP Acceleration & AI
Advanced Versal Adaptive SoC AI Engine \| Online	OL (Online Live)	Embedded Development	Online	3 days	Sep 22, 2025	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP Acceleration & AI
Advanced Versal Adaptive SoC AI Engine \| Online	OL (Online Live)	Embedded Development	Online	3 days	Dec 15, 2025	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP Acceleration & AI
UVM Testbench Made Easy	WO (Workshop)	Programming Languages		2 days	all year on request	Info FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions
UVM Testbench Made Easy \| Online	OL (Online Live)	Programming Languages	Online	2 days	all year on request	Info FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions
SystemVerilog Advanced Verification for FPGA Design	WO (Workshop)	Programming Languages		3 days	all year on request	Info FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis
SystemVerilog Advanced Verification for FPGA Design \| Online	OL (Online Live)	Programming Languages	Online	3 days	all year on request	Info FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis
Professional VHDL	PW (Power Workshop)	Programming Languages	Freiburg	5 days	Jul 21, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	PW (Power Workshop)	Programming Languages	Frankfurt / Main	5 days	Oct 06, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	PW (Power Workshop)	Programming Languages	Freiburg	5 days	Dec 15, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL \| Online	OL (Online Live)	Programming Languages	Online	5 days	Jul 21, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL \| Online	OL (Online Live)	Programming Languages	Online	5 days	Oct 06, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL \| Online	OL (Online Live)	Programming Languages	Online	5 days	Dec 15, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL Testbenches and Verification with OSVVM	PW (Power Workshop)	Programming Languages	Freiburg	5 days	Sep 08, 2025	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional VHDL Testbenches and Verification with OSVVM	PW (Power Workshop)	Programming Languages	Freiburg	5 days	Nov 17, 2025	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional VHDL Testbenches and Verification with OSVVM \| Online	OL (Online Live)	Programming Languages	Online	5 days	Sep 08, 2025	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional VHDL Testbenches and Verification with OSVVM \| Online	OL (Online Live)	Programming Languages	Online	5 days	Nov 17, 2025	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional Python for Embedded	PW (Power Workshop)	Programming Languages	Frankfurt / Main	5 days	Sep 22, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Professional Python for Embedded	PW (Power Workshop)	Programming Languages	Berlin	5 days	Nov 24, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Professional Python for Embedded \| Online	OL (Online Live)	Programming Languages	Online	5 days	Sep 22, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Professional Python for Embedded \| Online	OL (Online Live)	Programming Languages	Online	5 days	Nov 24, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact VHDL for Synthesis	WO (Workshop)	Programming Languages	Stuttgart	3 days	Sep 15, 2025	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Synthesis	WO (Workshop)	Programming Languages	Munich	3 days	Nov 03, 2025	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Synthesis \| Online	OL (Online Live)	Programming Languages	Online	3 days	Sep 15, 2025	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Synthesis \| Online	OL (Online Live)	Programming Languages	Online	3 days	Nov 03, 2025	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Simulation	WO (Workshop)	Programming Languages	Stuttgart	2 days	Sep 18, 2025	Info FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation
Compact VHDL for Simulation	WO (Workshop)	Programming Languages	Munich	2 days	Nov 06, 2025	Info FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation
Compact VHDL for Simulation \| Online	OL (Online Live)	Programming Languages	Online	2 days	Sep 18, 2025	Info FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation
Compact VHDL for Simulation \| Online	OL (Online Live)	Programming Languages	Online	2 days	Nov 06, 2025	Info FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation
Compact Python for Embedded	WO (Workshop)	Programming Languages	Frankfurt / Main	3 days	Sep 22, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact Python for Embedded	WO (Workshop)	Programming Languages	Berlin	3 days	Nov 24, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact Python for Embedded \| Online	OL (Online Live)	Programming Languages	Online	3 days	Sep 22, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact Python for Embedded \| Online	OL (Online Live)	Programming Languages	Online	3 days	Nov 24, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Designing with Ethernet MAC Controllers	WO (Workshop)	FPGA Connectivity & Protocols	Berlin	2 days	Sep 09, 2025	Info Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP
Designing with Ethernet MAC Controllers	WO (Workshop)	FPGA Connectivity & Protocols	Freiburg	2 days	Nov 20, 2025	Info Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP
Designing with Ethernet MAC Controllers \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	2 days	Sep 09, 2025	Info Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP
Designing with Ethernet MAC Controllers \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	2 days	Nov 20, 2025	Info Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP
Compact Zynq UltraScale+ RFSoC	WO (Workshop)	FPGA Connectivity & Protocols	Frankfurt / Main	3 days	Sep 22, 2025	Info RFSoC ADC DAC RF UltraScale+ Data Converter
Compact Zynq UltraScale+ RFSoC	WO (Workshop)	FPGA Connectivity & Protocols	Munich	3 days	Dec 01, 2025	Info RFSoC ADC DAC RF UltraScale+ Data Converter
Compact Versal Adaptive SoC: Power and Board Design	WO (Workshop)	FPGA Connectivity & Protocols		3 days	all year on request	Info Embedded ACAP board design integrity power Versal Cortex-A72 Cortex-R5 NoC DDR4 AXI XPE power design Power Supply PDM Signal Integrity Reflection Crosstalk IBIS
Compact Versal Adaptive SoC: Power and Board Design \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	3 days	all year on request	Info Embedded ACAP board design integrity power Versal Cortex-A72 Cortex-R5 NoC DDR4 AXI XPE power design Power Supply PDM Signal Integrity Reflection Crosstalk IBIS
Compact Versal Adaptive SoC: Connectivity	WO (Workshop)	FPGA Connectivity & Protocols	Frankfurt / Main	3 days	Aug 25, 2025	Info Versal High-Speed Interfaces ACAP 10GE 100GE 400GE MAC PCS FEC transceiver PLL hard IP Aurora DDR4 memory interface VCK190 Gigabit Ethernet
Compact Versal Adaptive SoC: Connectivity	WO (Workshop)	FPGA Connectivity & Protocols	Stuttgart	3 days	Nov 10, 2025	Info Versal High-Speed Interfaces ACAP 10GE 100GE 400GE MAC PCS FEC transceiver PLL hard IP Aurora DDR4 memory interface VCK190 Gigabit Ethernet
Compact Versal Adaptive SoC: Connectivity \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	3 days	Aug 25, 2025	Info Versal High-Speed Interfaces ACAP 10GE 100GE 400GE MAC PCS FEC transceiver PLL hard IP Aurora DDR4 memory interface VCK190 Gigabit Ethernet
Compact Versal Adaptive SoC: Connectivity \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	3 days	Nov 10, 2025	Info Versal High-Speed Interfaces ACAP 10GE 100GE 400GE MAC PCS FEC transceiver PLL hard IP Aurora DDR4 memory interface VCK190 Gigabit Ethernet
Compact UltraScale: Serial Transceivers	WO (Workshop)	FPGA Connectivity & Protocols	Frankfurt / Main	3 days	Sep 15, 2025	Info UltraScale Serial Transceiver GTX GTH GTY 8B/10B 64B/66B 64B/67B UltraScale+ gearbox PLL KCU105
Compact UltraScale: Serial Transceivers \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	3 days	Sep 15, 2025	Info UltraScale Serial Transceiver GTX GTH GTY 8B/10B 64B/66B 64B/67B UltraScale+ gearbox PLL KCU105
Compact UltraScale: High-Speed Memory Interfacing	WO (Workshop)	FPGA Connectivity & Protocols		3 days	all year on request	Info 7Series DDR3 memory Memory Controller PCB Design PCB Design Rules Debugging DDR3 UltraScale UltraScale+ DDR4 memory
Compact UltraScale: High-Speed Memory Interfacing \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	3 days	all year on request	Info 7Series DDR3 memory Memory Controller PCB Design PCB Design Rules Debugging DDR3 UltraScale UltraScale+ DDR4 memory
Compact UltraScale: Board Design and Signal Integrity	WO (Workshop)	FPGA Connectivity & Protocols		3 days	all year on request	Info UltraScale Power Supply board design power integrity Signal Integrity Reflection Crosstalk HyperLynx IBIS AMI Models PCB Simulation High-Speed Interfaces Transceiver PCI Express DDR4 PCB Design UltraScale+ board design power design Power Supply XPE Signal Integrity Reflection Crosstalk IBIS
Compact UltraScale: Board Design and Signal Integrity \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	3 days	all year on request	Info UltraScale Power Supply board design power integrity Signal Integrity Reflection Crosstalk HyperLynx IBIS AMI Models PCB Simulation High-Speed Interfaces Transceiver PCI Express DDR4 PCB Design UltraScale+ board design power design Power Supply XPE Signal Integrity Reflection Crosstalk IBIS
AXI Interface Technology	WO (Workshop)	FPGA Connectivity & Protocols	Berlin	2 days	Sep 11, 2025	Info FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance
AXI Interface Technology	WO (Workshop)	FPGA Connectivity & Protocols	Munich	2 days	Nov 06, 2025	Info FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance
AXI Interface Technology \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	2 days	Sep 11, 2025	Info FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance
AXI Interface Technology \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	2 days	Nov 06, 2025	Info FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance
Compact UltraScale: Integrated PCI Express Systems	WO (Workshop)	FPGA Connectivity & Protocols	Munich	3 days	Sep 01, 2025	Info UltraScale PCI Express Integrated Block for PCI Express Gen3 PL PCIe UltraScale+ PCIe endpoint root port DMA KCU105
Compact UltraScale: Integrated PCI Express Systems	WO (Workshop)	FPGA Connectivity & Protocols	Berlin	3 days	Dec 08, 2025	Info UltraScale PCI Express Integrated Block for PCI Express Gen3 PL PCIe UltraScale+ PCIe endpoint root port DMA KCU105
Compact UltraScale: Integrated PCI Express Systems \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	3 days	Sep 01, 2025	Info UltraScale PCI Express Integrated Block for PCI Express Gen3 PL PCIe UltraScale+ PCIe endpoint root port DMA KCU105
Compact UltraScale: Integrated PCI Express Systems \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	3 days	Dec 08, 2025	Info UltraScale PCI Express Integrated Block for PCI Express Gen3 PL PCIe UltraScale+ PCIe endpoint root port DMA KCU105
FPGA Designer (Long Term)	LT (Long Term Education)	Development Tools & Methodology	Freiburg	8 dates of 2 days each	Sep 09, 2025	Info
Embedded Designer (Long Term)	LT (Long Term Education)	Embedded Development	Freiburg	8 dates of 2 days each	Oct 01, 2025	Info
Compact Vivado Design Suite Tool Flow	WO (Workshop)	Development Tools & Methodology	Stuttgart	2 days	Sep 15, 2025	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
Compact Vivado Design Suite Tool Flow	WO (Workshop)	Development Tools & Methodology	Munich	2 days	Nov 17, 2025	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
Compact Vivado Design Suite Tool Flow \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Sep 15, 2025	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
Compact Vivado Design Suite Tool Flow \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Nov 17, 2025	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
Compact Timing Constraints and Analysis	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Sep 17, 2025	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis	WO (Workshop)	Development Tools & Methodology	Munich	3 days	Nov 19, 2025	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 17, 2025	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 19, 2025	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
FPGA Circuit Design Technique	SE (Seminar)	Development Tools & Methodology	Freiburg	1 day	Sep 24, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung IP Core
Professional Vivado	PW (Power Workshop)	Development Tools & Methodology	Frankfurt / Main	5 days	Jul 07, 2025	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Oct 20, 2025	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	PW (Power Workshop)	Development Tools & Methodology	Frankfurt / Main	5 days	Dec 01, 2025	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Jul 07, 2025	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Oct 20, 2025	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Dec 01, 2025	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vitis	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Aug 25, 2025	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT
Professional Vitis	PW (Power Workshop)	Development Tools & Methodology	Berlin	5 days	Nov 10, 2025	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT
Professional Vitis \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Aug 25, 2025	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT
Professional Vitis \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Nov 10, 2025	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT
Professional FPGA Circuit Design Technique	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Jul 07, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Nov 03, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Jul 07, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Nov 03, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Git for EDA Tool Flows	WO (Workshop)	Development Tools & Methodology	Munich	3 days	Sep 01, 2025	Info Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging
Git for EDA Tool Flows	WO (Workshop)	Development Tools & Methodology	Freiburg	3 days	Dec 08, 2025	Info Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging
Git for EDA Tool Flows \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 01, 2025	Info Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging
Git for EDA Tool Flows \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Dec 08, 2025	Info Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging
FPGA Power Optimization	WO (Workshop)	Development Tools & Methodology		2 days	all year on request	Info FPGA Power Vivado Kintex XCE clocking
FPGA Power Optimization \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	all year on request	Info FPGA Power Vivado Kintex XCE clocking
Easy Start FPGA Vivado	ES (Easy Start)	Development Tools & Methodology	Stuttgart	2 days	Aug 04, 2025	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Easy Start FPGA Vivado	ES (Easy Start)	Development Tools & Methodology	Frankfurt / Main	2 days	Nov 13, 2025	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Easy Start FPGA Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Aug 04, 2025	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Easy Start FPGA Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Nov 13, 2025	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Dynamic Function eXchange (DFX)	WO (Workshop)	Development Tools & Methodology	Stuttgart	2 days	Jul 24, 2025	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Dynamic Function eXchange (DFX)	WO (Workshop)	Development Tools & Methodology	Freiburg	2 days	Oct 16, 2025	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Dynamic Function eXchange (DFX) \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Jul 24, 2025	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Dynamic Function eXchange (DFX) \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Oct 16, 2025	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Debugging Techniques Using the Vivado Logic Analyzer	WO (Workshop)	Development Tools & Methodology	Stuttgart	2 days	Sep 11, 2025	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Debugging Techniques Using the Vivado Logic Analyzer	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	2 days	Dec 08, 2025	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Debugging Techniques Using the Vivado Logic Analyzer \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Sep 11, 2025	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Debugging Techniques Using the Vivado Logic Analyzer \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Dec 08, 2025	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Continuous Integration for EDA Tools	PW (Power Workshop)	Development Tools & Methodology	Frankfurt / Main	5 days	Jul 14, 2025	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Continuous Integration for EDA Tools	PW (Power Workshop)	Development Tools & Methodology	Berlin	5 days	Oct 20, 2025	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Continuous Integration for EDA Tools \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Jul 14, 2025	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Continuous Integration for EDA Tools \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Oct 20, 2025	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Compact Vitis for the Software Designer	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	Sep 09, 2025	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
Compact Vitis for the Software Designer	WO (Workshop)	Development Tools & Methodology	Munich	3 days	Dec 17, 2025	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
Compact Vitis for the Software Designer \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 09, 2025	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
Compact Vitis for the Software Designer \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Dec 17, 2025	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
Compact Vitis for Acceleration	WO (Workshop)	Development Tools & Methodology	Freiburg	3 days	Aug 18, 2025	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging
Compact Vitis for Acceleration	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	Nov 03, 2025	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging
Compact Vitis for Acceleration \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Aug 18, 2025	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging
Compact Vitis for Acceleration \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 03, 2025	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging
NEW \| Compact Edge IoT	WO (Workshop)	Embedded Development	Berlin	3 days	Sep 09, 2025	Info edge ai design flow vitis Vivado phyton AMD adaptive socs alveo cards deep neural networks zynq ultrascale+ mpsoc
NEW \| Compact Edge IoT	WO (Workshop)	Embedded Development	Frankfurt / Main	3 days	Dec 03, 2025	Info edge ai design flow vitis Vivado phyton AMD adaptive socs alveo cards deep neural networks zynq ultrascale+ mpsoc
NEW \| Compact Edge IoT \| Online	OL (Online Live)	Embedded Development	Online	3 days	Sep 09, 2025	Info edge ai design flow vitis Vivado phyton AMD adaptive socs alveo cards deep neural networks zynq ultrascale+ mpsoc
NEW \| Compact Edge IoT \| Online	OL (Online Live)	Embedded Development	Online	3 days	Dec 03, 2025	Info edge ai design flow vitis Vivado phyton AMD adaptive socs alveo cards deep neural networks zynq ultrascale+ mpsoc
NEW \| Compact Edge AI Application Design Flow	WO (Workshop)	Development Tools & Methodology	Munich	3 days	Sep 15, 2025	Info edge ai design flow vitis Vivado phyton AMD adaptive socs alveo cards deep neural networks zynq ultrascale+ mpsoc
NEW \| Compact Edge AI Application Design Flow	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Nov 19, 2025	Info edge ai design flow vitis Vivado phyton AMD adaptive socs alveo cards deep neural networks zynq ultrascale+ mpsoc
NEW \| Compact Edge AI Application Design Flow \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 15, 2025	Info edge ai design flow vitis Vivado phyton AMD adaptive socs alveo cards deep neural networks zynq ultrascale+ mpsoc
NEW \| Compact Edge AI Application Design Flow \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 19, 2025	Info edge ai design flow vitis Vivado phyton AMD adaptive socs alveo cards deep neural networks zynq ultrascale+ mpsoc
Compact Vitis AI	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Sep 01, 2025	Info Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software
Compact Vitis AI	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	Nov 10, 2025	Info Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software
Compact Vitis AI \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 01, 2025	Info Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software
Compact Vitis AI \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 10, 2025	Info Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software
Compact FPGA Circuit Design Technique	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Aug 06, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Compact FPGA Circuit Design Technique	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	Oct 15, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Compact FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Aug 06, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Compact FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Oct 15, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Compact Vitis HLS	WO (Workshop)	DSP & Image Processing	Freiburg	3 days	Aug 11, 2025	Info Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface
Compact Vitis HLS	WO (Workshop)	DSP & Image Processing	Stuttgart	3 days	Nov 19, 2025	Info Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface
Compact Vitis HLS \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	Aug 11, 2025	Info Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface
Compact Vitis HLS \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	Nov 19, 2025	Info Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface
Professional DSP Design Using Vitis Model Composer	PW (Power Workshop)	DSP & Image Processing	Freiburg	5 days	Sep 01, 2025	Info DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox
Professional DSP Design Using Vitis Model Composer	PW (Power Workshop)	DSP & Image Processing	Berlin	5 days	Dec 15, 2025	Info DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox
Professional DSP Design Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	5 days	Sep 01, 2025	Info DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox
Professional DSP Design Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	5 days	Dec 15, 2025	Info DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox
Compact DSP Design for Versal Using Vitis Model Composer	WO (Workshop)	DSP & Image Processing		3 days	all year on request	Info DSP Mathworks Matlab Tool Flow FPGA
Compact DSP Design for Versal Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	all year on request	Info DSP Mathworks Matlab Tool Flow FPGA
Compact DSP Design for FPGAs Using Vitis Model Composer	WO (Workshop)	DSP & Image Processing	Freiburg	3 days	Sep 01, 2025	Info DSP Mathworks Matlab Tool Flow FPGA
Compact DSP Design for FPGAs Using Vitis Model Composer	WO (Workshop)	DSP & Image Processing	Berlin	3 days	Dec 15, 2025	Info DSP Mathworks Matlab Tool Flow FPGA
Compact DSP Design for FPGAs Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	Sep 01, 2025	Info DSP Mathworks Matlab Tool Flow FPGA
Compact DSP Design for FPGAs Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	Dec 15, 2025	Info DSP Mathworks Matlab Tool Flow FPGA
Zynq 7000 SoC for the System Architect	WO (Workshop)	AMD Architecture		2 days	all year on request	Info Embedded Architecture Vivado Vitis Zynq SoC Peripherals Memory
Zynq 7000 SoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	all year on request	Info Embedded Architecture Vivado Vitis Zynq SoC Peripherals Memory
Zynq UltraScale+ MPSoC for the System Architect	WO (Workshop)	AMD Architecture	Freiburg	2 days	Sep 29, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE
Zynq UltraScale+ MPSoC for the System Architect	WO (Workshop)	AMD Architecture	Munich	2 days	Dec 15, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE
Zynq UltraScale+ MPSoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Sep 29, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE
Zynq UltraScale+ MPSoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Dec 15, 2025	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE
Versal Adaptive SoC for the System Architect	WO (Workshop)	AMD Architecture	Stuttgart	2 days	Aug 21, 2025	Info Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI
Versal Adaptive SoC for the System Architect	WO (Workshop)	AMD Architecture	Munich	2 days	Nov 17, 2025	Info Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI
Versal Adaptive SoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Aug 21, 2025	Info Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI
Versal Adaptive SoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Nov 17, 2025	Info Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI
Professional FPGA	PW (Power Workshop)	AMD Architecture	Freiburg	5 days	Jul 14, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA	PW (Power Workshop)	AMD Architecture	Munich	5 days	Oct 20, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA \| Online	OL (Online Live)	AMD Architecture	Online	5 days	Jul 14, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA \| Online	OL (Online Live)	AMD Architecture	Online	5 days	Oct 20, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Essentials of Microprocessors	WO (Workshop)	AMD Architecture		1 day	all year on request	Info Embedded Microcontroller Processor Compiler Cache Linker Debugger Vitis
Essentials of Microprocessors \| Online	OL (Online Live)	AMD Architecture	Online	1 day	all year on request	Info Embedded Microcontroller Processor Compiler Cache Linker Debugger Vitis
Compact UltraScale/UltraScale+	WO (Workshop)	AMD Architecture	Frankfurt / Main	2 days	Sep 25, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+	WO (Workshop)	AMD Architecture	Stuttgart	2 days	Nov 24, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+ \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Sep 25, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+ \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Nov 24, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact FPGA 7 Series	WO (Workshop)	AMD Architecture		2 days	on request all year tbd	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP 7 series IO
Compact FPGA 7 Series \| Online	OL (Online Live)	AMD Architecture	Online	2 days	all year on request	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP 7 series IO
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TRAINING and CONSULTING ON THE JOB

Apply Your Learning Successfully on Your Current Project.

PLC2 unique »training on the job« provides you with onsite training during the development of your projects. In addition to the theoretical training by one of our experienced speakers, your current tasks and solutions are worked out at the same time resulting into a reduced development time.

Unexpected problems during the midst of a development are every engineer nightmare. We at PLC2 are here to help and consult you onsite to work out together a solution to your problems and help you achieve your deadlines.

Contact us below for further Information.

What Our Customers Are Saying

»PLC2 has consistently demonstrated top-notch expertise in the realm of FPGA training and design reviews. Their team’s dedication and proficiency have made them our primary choice. We couldn’t be happier with the outcomes and insights they’ve provided.«

Arthur Bebernik

R&D Senior Engineer Hardware

ABB

»We at SCIENION, a global leader in Precision Cell Dispensing are continuously improving our products to include leading-edge technologies. With PLC2, we found a partner to reach our goals. PLC2 has a highly skilled staff in FPGA/SoC-related competencies and helped us complete our project successfully on time. PLC2 will definitely be our partner for the next technical challenges.«

Tarik Salt

Electronics Engineer

SCIENION GmbH

»As a recent graduate, I learned at PLC2 not only the basics about FPGAs and VHDL, but also the proper use of Vivado. The trainings have sustainably improved my work and I still benefit from them today. Due to the wide knowledge, PLC2 is also the right contact for detailed technical questions about Xilinx products.«

Konstantin Wagner

Software Engineer Power Electronics

Maschinenfabrik Reinhausen GmbH

»PLC2 is a competent partner in all areas related to FPGA design. The workshops and seminars offered cover the entire spectrum of the FPGA world and they are also available at any time for specific project-related support.«

Thomas Donner

Management Center Elektronik (MCE)

Stöber Antriebstechnik GmbH & Co. KG

»We did our recent FPGA project in collaboration with PLC2. Our team was very satisfied with their expertise in FPGA design, their availability and responsiveness throughout the project which finally made the project a success. We highly recommend them to anyone looking for reliable and knowledgeable service providers. Thank you, PLC2, for your contribution to our project!«

Dr. Lothar Springob

System Integration Manager

Bonfiglioli Vectron GmbH

»We have been customer of PLC2 for many years and have enjoyed the friendly and competent way of working with them. PLC2 is therefore still our first contact when we need training on special FPGA topics. Frequently, we have also enjoyed in-house visits from PLC2, where we have received training, consulting and design reviews tailored to our needs. Also, the annual FPGA conference is a very good opportunity to get an insight into current FPGA trends and to exchange experiences with other FPGA developers.«

Stefan Eiermann

Electronics Hardware Principal Technical Expert

Schneider Electric Automation GmbH

*30 % on second booking:

Offer is valid until 31.12.2025, but not for in-house training or for the payment with TCs. Only available for the same public training course from the second booking onwards.

How can we help?

Contact

Call PLC2

+49 7664 91313-15

Send an e-mail

michael.schwarz@plc2.de

FAQ

01. Can you help me with reserving the room?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

02. What times in the day do courses start and end?

Our face-to-face and online courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours.

03. Are course materials provided?

All participants of paid courses will receive English training materials in electronic or paper form.

04. Will I receive a course certificate?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

05. Can I pay with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

06. What are the options for payment?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

07. What is the deadline for payment?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

08. What are the options for cancelling?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

09. When will I receive a firm commitment as to whether the course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

10. How many participants are required for a course to be given/what is the minimum number of participants?

We generally offer courses for 5 or more people. That means that if you would like to book a course at your premises, you need 5 people to register or need to pay the amount for 5 participants, even if fewer people attend.

11. Can I book a course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

12. What language is the course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.

Technical Training in a Renowned Training Center

PLC2 Training Courses Around FPGAs, SoCs, MPSoCs, Programming Languages, and More

PLC2 Training Calendar 2025 Bring your colleagues to your next training. Up from the second booking of the same training course you will save 30 %.*

All Trainings

Apply Your Learning Successfully on Your Current Project.

PLC2 Training Calendar 2025
Bring your colleagues to your next training. Up from the second booking of the same training course you will save 30 %.*