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PLC2 Training Format

Intensive 5-Day Power Workshops around FPGAs, MPSoCs, Embedded Solutions, and more

In the five-day Power Workshops, our experts provide developers with particularly hands-on training in technical depth. Here, care is taken to ensure that the knowledge imparted is consolidated in the form of practical exercises.
Under the guidance and supervision of our competent trainers, the participants work intensively with laptops/PCs and, if required, with evaluation boards. Complex tasks are implemented, and the functionality is proven with the help of the simulation and the evaluation board.
The Power Workshops are suitable for all those who want to delve deeply into a topic and attach a lot of importance to practical relevance.

Power Workshop in a Nutshell

Be the first to learn from the experts

As an authorized training provider PLC2 is the first to have access to the latest AMD Xilinx technologies, design methods, and tools.
01

Extensive four or five days workshop

Our experts provide developers with particularly hands-on training in deep technical depth, making sure that the learned knowledge is consolidated in the form of practical exercises.
02

Practice-oriented

Under the guidance and supervision of our experts, the participants work intensively on laptops and evaluation boards.
03

Become an expert yourself

The Power Workshops are targeted at all those that want to dig deeply into a specific topic and appreciate the practical relevance.
04

Upcoming Power Workshops

Course Format Category Location Duration Date

Professional Versal Adaptive SoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

5 days

Jun 10, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI

Professional Versal Adaptive SoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

5 days

Sep 02, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI

Professional Versal Adaptive SoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Stuttgart

5 days

Nov 11, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI

Professional Zynq 7000 SoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

5 days

all year on request

Info

Embedded Architecture Vivado Vitis Zynq SoC Boot Software C C++ AXI Configuration System Integration Debugging AXI

Professional Zynq UltraScale+ MPSoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

5 days

Jun 03, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Professional Zynq UltraScale+ MPSoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

5 days

Sep 16, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Professional Zynq UltraScale+ MPSoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

5 days

Dec 02, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Professional MicroBlaze System Design

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

5 days

all year on request

Info

Embedded Vitis softcore driver c c++ Vivado processor microcontroller core MicroBlaze Architecture Cache Workflow Platform AXI Peripherals Vivado

Expert Zynq 7000 SoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

5 days

all year on request

Info

Embedded Architecture Vivado Vitis SoC Cortex-A9 Processor Cache PetaLinux IP-Integrator Linux PS AXI

Expert Versal Adaptive SoC AI Engine

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

5 days

Apr 22, 2024

Info

Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP , Acceleration & AI

Expert Versal Adaptive SoC AI Engine

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Munich

5 days

Jul 22, 2024

Info

Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP , Acceleration & AI

Expert Versal Adaptive SoC AI Engine

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

5 days

Oct 07, 2024

Info

Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP , Acceleration & AI

Professional VHDL

PW (Power Workshop)

Programming Languages

Munich

5 days

Apr 22, 2024

Info

FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis

Professional VHDL

PW (Power Workshop)

Programming Languages

Freiburg

5 days

Jul 22, 2024

Info

FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis

Professional VHDL

PW (Power Workshop)

Programming Languages

Frankfurt / Main

5 days

Oct 21, 2024

Info

FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis

Professional VHDL

PW (Power Workshop)

Programming Languages

Freiburg

5 days

Dec 02, 2024

Info

FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis

Professional VHDL Testbenches and Verification with OSVVM

PW (Power Workshop)

Programming Languages

Freiburg

5 days

Jun 24, 2024

Info

FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI

Professional VHDL Testbenches and Verification with OSVVM

PW (Power Workshop)

Programming Languages

Freiburg

5 days

Sep 16, 2024

Info

FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI

Professional VHDL Testbenches and Verification with OSVVM

PW (Power Workshop)

Programming Languages

Stuttgart

5 days

Nov 18, 2024

Info

FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI

Professional Python for Embedded

PW (Power Workshop)

Programming Languages

Freiburg

5 days

Jun 24, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Professional Python for Embedded

PW (Power Workshop)

Programming Languages

Frankfurt / Main

5 days

Sep 23, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Professional Python for Embedded

PW (Power Workshop)

Programming Languages

Berlin

5 days

Nov 25, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Professional Vivado

PW (Power Workshop)

Development
Tools & Methodology

Frankfurt / Main

5 days

Jul 22, 2024

Info

Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary

Professional Vivado

PW (Power Workshop)

Development
Tools & Methodology

Freiburg

5 days

Oct 07, 2024

Info

Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary

Professional Vivado

PW (Power Workshop)

Development
Tools & Methodology

Frankfurt / Main

5 days

Dec 09, 2024

Info

Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary

Professional Vitis

PW (Power Workshop)

Development
Tools & Methodology

Stuttgart

5 days

Jun 24, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT

Professional Vitis

PW (Power Workshop)

Development
Tools & Methodology

Freiburg

5 days

Aug 05, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT

Professional Vitis

PW (Power Workshop)

Development
Tools & Methodology

Berlin

5 days

Nov 04, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT

Professional FPGA Circuit Design Technique

PW (Power Workshop)

Development
Tools & Methodology

Freiburg

5 days

Apr 08, 2024

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+

Professional FPGA Circuit Design Technique

PW (Power Workshop)

Development
Tools & Methodology

Freiburg

5 days

Jul 15, 2024

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+

Professional FPGA Circuit Design Technique

PW (Power Workshop)

Development
Tools & Methodology

Freiburg

5 days

Nov 04, 2024

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+

Continuous Integration for EDA Tools

PW (Power Workshop)

Development
Tools & Methodology

Freiburg

5 days

May 13, 2024

Info

FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL

Continuous Integration for EDA Tools

PW (Power Workshop)

Development
Tools & Methodology

Frankfurt / Main

5 days

Jul 08, 2024

Info

FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL

Continuous Integration for EDA Tools

PW (Power Workshop)

Development
Tools & Methodology

Berlin

5 days

Oct 07, 2024

Info

FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL

Professional DSP Design Using Vitis Model Composer

PW (Power Workshop)

DSP & Image Processing

Frankfurt / Main

5 days

Apr 08, 2024

Info

DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox

Professional DSP Design Using Vitis Model Composer

PW (Power Workshop)

DSP & Image Processing

Freiburg

5 days

Sep 02, 2024

Info

DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox

Professional DSP Design Using Vitis Model Composer

PW (Power Workshop)

DSP & Image Processing

Berlin

5 days

Dec 16, 2024

Info

DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox

Professional FPGA

PW (Power Workshop)

AMD FPGA & (Adaptive) SoC & MPSoC Architecture

Frankfurt / Main

5 days

May 13, 2024

Info

FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC

Professional FPGA

PW (Power Workshop)

AMD FPGA & (Adaptive) SoC & MPSoC Architecture

Freiburg

5 days

Jul 08, 2024

Info

FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC

Professional FPGA

PW (Power Workshop)

AMD FPGA & (Adaptive) SoC & MPSoC Architecture

Munich

5 days

Oct 21, 2024

Info

FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC

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How can we help?

Contact

FAQ

01. Can you help me with reserving the room?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

02. What times in the day do courses start and end?

Our face-to-face courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours. For online courses, the start is also at 9 a.m. (CET/CEST), but they end at 2:30 p.m.. The total course time per day is 4 and a half hours plus breaks.

03. Are course materials provided?

All participants of paid courses will receive English training materials in electronic or paper form.

04. Will I receive a course certificate?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

05. Can I pay with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

06. What are the options for payment?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

07. What is the deadline for payment?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

08. What are the options for cancelling?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

09. When will I receive a firm commitment as to whether the course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

10. How many participants are required for a course to be given/what is the minimum number of participants?

We generally offer courses for 5 or more people. That means that if you would like to book a course at your premises, you need 5 people to register or need to pay the amount for 5 participants, even if fewer people attend.

11. Can I book a course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

12. What language is the course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.