PLC2 Training

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

In today’s competitive world of electronic engineering the difference is made at the system architectural level. Making the right choices at the start of your design makes the difference between mediocre versus excellent results. We at PLC2 can help you by providing training courses in the architecture area of the world’s leading FPGAs from AMD. The workshops provide the foundation you need to get started with your FPGA development or to optimize your FPGA designs. Our classes are suited for both FPGA newcomers and experienced developers.

Upcoming Trainings

Course	Format	Category	Location	Duration	Date
Mastering Clock Domain Crossing: Strategies for Synchronization and Stability	WE (Webinar)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	1 hour	on demand	Info clock domain crossing AMDF FPGA FPGAs metastability synchronizers MTBF signal synchronization AMD webinar
FPGA Circuit Design Part 2: Interfaces and Best Practices	WE (Webinar)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	1 hour	on demand	Info FPGA Circuit Design designs synchronous asynchronous design techniques technique designing state machines machine AMD webinar
FPGA Circuit Design Part 1: Synchronous and Asynchronous Design Techniques	WE (Webinar)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	1 hour	on demand	Info FPGA Circuit Design designs synchronous asynchronous design techniques technique, designing state machines machine AMD
Developing Demanding Applications with Versal Adaptive SoCs	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	1 day	the whole year tbd	Info Seminar Versal Adaptive SoC Vitis Unififed Development Platform design integration
Understanding Versal: The Adaptable Engines	WE (Webinar)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	1 hour	on demand	Info Versal, AI, Zynq, MPSoC
Understanding Versal: The DSP Engines	WE (Webinar)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	1 hour	on demand	Info Versal, AI, Zynq, MPSoC
Understanding Versal: The AI Engine	WE (Webinar)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	1 hour	on demand	Info Versal, AI, Zynq, MPSoC
Understanding Versal: Scalar Engines - The Processing System	WE (Webinar)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	1 hour	on demand	Info Versal, AI, Zynq, MPSoC
Understanding Versal: The Architecture	WE (Webinar)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	1 hour	on demand	Info Versal, AI, Zynq, MPSoC
Understanding Versal: Versal vs. Zynq MPSoC	WE (Webinar)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	1 hour	on demand	Info Versal, AI, Zynq, MPSoC
Zynq 7000 SoC for the System Architect	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture		2 days	all year on request	Info Embedded Architecture Vivado Vitis Zynq SoC Peripherals Memory
Zynq 7000 SoC for the System Architect	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture		2 days	all year on request	Info Embedded Architecture Vivado Vitis Zynq SoC Peripherals Memory
Zynq UltraScale+ MPSoC for the System Architect	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Frankfurt / Main	2 days	Jun 03, 2024	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE
Zynq UltraScale+ MPSoC for the System Architect	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Freiburg	2 days	Sep 12, 2024	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE
Zynq UltraScale+ MPSoC for the System Architect	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Munich	2 days	Dec 19, 2024	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE
Zynq UltraScale+ MPSoC for the System Architect	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	2 days	Nov 20, 2024	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE
Versal Adaptive SoC for the System Architect	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Stuttgart	2 days	Aug 01, 2024	Info Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI
Versal Adaptive SoC for the System Architect	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Munich	2 days	Nov 18, 2024	Info Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI
Versal Adaptive SoC for the System Architect	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	2 days	Dec 11, 2024	Info Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI
Professional FPGA	PW (Power Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Frankfurt / Main	5 days	May 13, 2024	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA	PW (Power Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Freiburg	5 days	Jul 08, 2024	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA	PW (Power Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Munich	5 days	Oct 21, 2024	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	5 days	Oct 21, 2024	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Essentials of Microprocessors	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture		1 day	all year on request	Info Embedded Microcontroller Processor Compiler Cache Linker Debugger Vitis
Essentials of Microprocessors	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture		1 day	all year on request	Info Embedded Microcontroller Processor Compiler Cache Linker Debugger Vitis
Compact UltraScale/UltraScale+	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Freiburg	2 days	Jun 24, 2024	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Frankfurt / Main	2 days	Sep 26, 2024	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Stuttgart	2 days	Nov 21, 2024	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	2 days	Oct 28, 2024	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact FPGA 7 Series	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture		2 days	on request all year tbd	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP 7 series IO
Compact FPGA 7 Series	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture		2 days	all year on request	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP 7 series IO
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Training Formats

Online Live

Online course
In-depth exercises in self-study

EXPLORE

Webinar

Good overview of a topic
Technical focus
Online

EXPLORE

Seminar

1-day technical deep dive
Free of charge
For developers, department heads, and managers

EXPLORE

Easy Start

Perfect for beginners and project managers
With a focus on practical exercises

EXPLORE

Workshop

Compact 2- or 3-day workshop
Ideal for developers
Theory and practice

EXPLORE

Power Workshop

4 or 5 days
Very extensive further training
Practice-oriented on PC and evaluation board
Detailed treatment of technical topics

EXPLORE

Long Term Education

3 months training
For engineers and technicians
Including comprehensive training material

EXPLORE

More PLC2 Training
Categories

Development
Tools & Methodology

The HDL based development method simplifies the development cycle, but this requires the developer to have good knowledge of digital circuit design.

Learn more

Programming Languages

Familiarize yourself with the latest design methods to get the most out of your chosen technology. Learn the fundamentals and become an expert in HDL languages such as VHDL or System Verilog.

Learn more

Embedded for AMD (Adaptive) SoCs & MPSoCs

Are you a beginner in the embedded world or a very experienced embedded developer, we at PLC2 tailor our embedded classes to your level. Our workshops include everything you need to know on how to develop embedded solutions with AMD's wide range of SoCs.

Learn more

DSP & Image Processing

With their inherent flexibility, AMD FPGAs and SoCs are ideal for high-performance or multi-channel digital signal processing (DSP) applications that can take advantage of hardware parallelism.

Learn more

Connectivity

How do you keep up with the edge network emerging applications that are redefining hardware requirements for electronic designers? Are you designing the next generation AI for IoT, embedded vision, hardware security, 5G communication or industrial/automotive automation for your company?

Learn more

How can we help?

Contact

Call PLC2

+49 7664 91313-15

Send an e-mail

michael.schwarz@plc2.de

FAQ

01. Can you help me with reserving the room?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

02. What times in the day do courses start and end?

Our face-to-face courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours. For online courses, the start is also at 9 a.m. (CET/CEST), but they end at 2:30 p.m.. The total course time per day is 4 and a half hours plus breaks.

03. Are course materials provided?

All participants of paid courses will receive English training materials in electronic or paper form.

04. Will I receive a course certificate?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

05. Can I pay with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

06. What are the options for payment?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

07. What is the deadline for payment?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

08. What are the options for cancelling?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

09. When will I receive a firm commitment as to whether the course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

10. How many participants are required for a course to be given/what is the minimum number of participants?

We generally offer courses for 5 or more people. That means that if you would like to book a course at your premises, you need 5 people to register or need to pay the amount for 5 participants, even if fewer people attend.

11. Can I book a course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

12. What language is the course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.