Open-Source VHDL
IP Core Library

As a comprehensive open-source library of synthesizable IP cores, designed for FPGA and ASIC development, the PoC-Library supports a wide range of FPGA devices from different vendors.

With its strong focus on flexibility, portability, performance, and usability, you are provided with a solid foundation for building reliable, scalable, and vendor-neutral designs.

Open-Source Know-How at PLC2:
From Training to Development

PLC2 has over eight years of experience working with open-source technologies, which we use in our training sessions and daily project work.

The key tool in this context is the Pile of Cores (PoC), an open-source framework whose goals align closely with PLC2’s design and architecture philosophy. By using the library in nearly all of our customer projects and PLC2 products, we have gained independence from vendor-specific IP cores.

GitHub Repository

Documentation

PLC2’s Contribution

Modifications

Bug fixes in existing moduls.
New generics and modes for preexisting modules.

AXI4

– FIFO and variants
– Clock Domain Crossing
– AXI4 to AXI4-Lite Adapter

AXI4-Lite

– FIFO
– Clock Domain Crossing
– Generic Register

AXI4-Stream

– FIFO and variants
– Clock Domain Crossing
– Multiplexer / Demultiplexer
– Stage

PoC-Library part I

Open-Source VHDL Component Library »Pile of Cores«

Poc-Library part II

Hands-On: Using Axi4Lite_Register in Vivado

PoC-Library part III

Solving All CDC Problems with a Handful of Components

PoC Release 2.0

With years of internal development of the PoC-Library to meet our own and our customers’ needs, the internal fork has been constantly grown and matured. Most additions focus on the AXI bus infrastructure to replace standard IP cores from the Vivado™ toolchain. This effort enabled PLC2 with higher flexibility, less resource consumption, and better development insights while debugging.

In collaboration with the public PoC maintainers our contributions have been reviewed and accepted and the PoC-Library made a version increment from 1.2. to 2.0.

To highlight one of our key developments, we present our AXI4-Lite register which is purely written in VHDL-2008. The generic register is synthesized from a register description array acting as a single source of truth.

The UART example demonstrates a simple, four register UART interface, mimicking the AMD (former Xilinx) AXI-Lite UART IP core – clean, concise, and easy to follow.

Mimicking AXI-Lite UART interface

Open-Source VHDL IP Core Library

Open-Source VHDL
IP Core Library