The PLC2 lossless, low latency, low power, and lightweight L5 (De-)Compression IP is a compression IP for modern data acquisition and processing systems. Special features make it possible to integrate the (de-)compression IP in existing AMD FPGA-based designs and thus save time and costs.
The L5 (De-)Compression IP can achieve state-of-the-art subframe latency and low power consumption, without the need to invest in new and powerful hardware. Additional benefits include lightweight implementation in terms of resource consumption and lossless decompression for a wide range of applications at the edge and in the cloud.
With this unique combination of assets, this core can be easily integrated into various scenarios, such as camera-based applications in the automotive industry, railway applications, robots, and/or drones. L5 reduces system storage costs, without adding significant latency to the overall system, and can reduce bandwidth needs at low power consumption.
Reduced storage costs
Extended fleet time on the road
Flexible integration into existing solutions – from edge to cloud, from FPGA-accelerated to software processed
Integrated in the whole product chain for acquisition and replay
Lower bandwidth expenses
Support for multiple image types and architectures
Lossless compression to maintain full precision
Most applications have a strong requirement for not losing a single bit within an image to ensure correct behavior of the attached system, like reaction on objects and the reaction time; losing a frame which is a keyframe in a multi-frame compression, like H.265 is leading to missed scenes or wrong measures. We at PLC2 see a camera as a sensor and the image as a measure. All changes to the measure are also changing the reaction, which is then based on a wrong assumption. L5 Compression is truly Lossless to prevent issues in that manner.
Integrating a module into an existing image processing chain or a transmission chain is a challenge by nature. If using an FPGA in addition, the integration into an existing design where the placement has already been done can be hard if the addition consumes a lot of resources. We designed the L5 Compression IP to have standard interfaces like AXI4-Stream and to be compatible with the AXI4-Stream Video Protocol of AMD. In addition, the resource usage is quite small to fit even into the smallest FPGAs and is easily adaptable for different architectures as it also does not require external resources like DDR memory.
Current trends are to reduce the power footprint of the applications to get most applications battery powered. Using the L5 Compression IP with its small resource usage makes it optimal for all applications needing lossless image compression without spending an additional power-consuming chip or requiring power-expensive external memory accesses.
Various applications like ADAS systems, control tasks in robotics and live transmissions where some reactions are being taken require low latency to reflect the scene at the reaction side (algorithm, operator, etc.) as fast as possible. A scenario where e. g. a child is visualized on the screen to appear while driving backwards with a car after a crash happens is not desired and can only be prevented if the system using image compression has low latency. We at PLC2 believe in that and have designed our L5 core to have a latency of below one frame time for the whole transmission chain (encoding and decoding together). We can achieve that in addition without the need for external memory.
* Resolution: 2.4 MP, 16 bpp / processing at 100 MHz with 2 pixel per beat / on own data-set
~ 30 % – 70 %
< 0.05 W
< 1 frame
Bayer Pattern (RCCG, RGGB, RCCC, etc.)
Up to 16 bit
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