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Familiarize yourself with the latest design methods to get the most out of your chosen technology. Learn the fundamentals and become an expert in HDL languages such as VHDL or System Verilog.
We offer a variety of workshops and training sessions to introduce you to System Verilog HDL and VHDL. You will learn the VHDL synthesis and simulation concept and understand how to use different synthesis or simulation constructs to design your FPGA.

Upcoming Trainings

Course Format Category Location Duration Date

VHDL Circuit Simulation Part 2: Stimulus Generation and Behavior Verification

WE (Webinar)

Languages

Online

11-12 am CEST

Jul 23, 2024

Info

VHDL circuit simulation simulations FPGA AMD webinar

VHDL Circuit Simulation Part 1: Behavior Modeling, Timing, and File I/O

WE (Webinar)

Languages

Online

11-12 am CEST

Jun 27, 2024

Info

VHDL circuit simulation simulations FPGA AMD webinar

VHDL Circuit Design Part 2: Advanced Concepts and Behavioral Modeling

WE (Webinar)

Languages

Online

11-12 am CEST

May 23, 2024

Info

VHDL circuit design designs application applications behavioral modeling AMD webinar

VHDL Circuit Design Part 1: Fundamentals and Methodologies

WE (Webinar)

Languages

Online

11-12 am CEST

Apr 24, 2024

Info

VHDL circuit design designs application applications AMD webinar HDL hardware design

Partially Constrained Record Types in VHDL-2008 Or: How to Wire Components Effectively?

WE (Webinar)

Languages

Online

1 hour

on demand

Info

VHDL, VHDL-2008, partially constrained types

Circuit Synthesis with VHDL

SE (Seminar)

Languages

Frankfurt / Main

1 day

Apr 09, 2024

Info

FPGA HDL VHDL HDL Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream

Circuit Synthesis with VHDL

SE (Seminar)

Languages

Stuttgart

1 day

Oct 15, 2024

Info

FPGA HDL VHDL HDL Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream

Circuit Simulation with VHDL

SE (Seminar)

Languages

Freiburg

1 day

May 22, 2024

Info

FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation

Circuit Simulation with VHDL

SE (Seminar)

Languages

Frankfurt / Main

1 day

Nov 13, 2024

Info

FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation

NEW | Compact SystemVerilog for Synthesis

WO (Workshop)

Languages

Frankfurt/Main

3 days

Apr 08, 2024

Info

FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis

NEW | Compact SystemVerilog for Synthesis

WO (Workshop)

Languages

Freiburg

3 days

Jul 10, 2024

Info

FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis

NEW | Compact SystemVerilog for Synthesis

WO (Workshop)

Languages

Munich

3 days

Oct 07, 2024

Info

FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis

NEW | Compact SystemVerilog for Synthesis

OL (Online Live)

Languages

Online

3 days

Apr 03, 2024

Info

FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis

NEW | Compact SystemVerilog for Synthesis

OL (Online Live)

Languages

Online

3 days

Nov 27, 2024

Info

FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis

Compact Verilog

WO (Workshop)

Languages

3 days

all year on request

Info

FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis

Compact Verilog

OL (Online Live)

Languages

3 days

all year on request

Info

FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis

NEW | Advanced VHDL

OL (Online Live)

Languages

Online

3 days

May 27, 2024

Info

Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool

NEW | Advanced VHDL

OL (Online Live)

Languages

Online

3 days

Dec 16, 2024

Info

Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool

NEW | Advanced VHDL

WO (Workshop)

Languages

Stuttgart

3 days

Mar 25, 2024

Info

Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool

NEW | Advanced VHDL

WO (Workshop)

Languages

Frankfurt

3 days

Jul 15, 2024

Info

Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool

NEW | Advanced VHDL

WO (Workshop)

Languages

Freiburg

3 days

Oct 28, 2024

Info

Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool

NEW | Advanced VHDL

WO (Workshop)

Languages

Munich

3 days

Dec 09, 2024

Info

Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool

Compact VHDL Testbenches and Verification with OSVVM

WO (Workshop)

Languages

Stuttgart

3 days

Mar 11, 2024

Info

FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator

Compact VHDL Testbenches and Verification with OSVVM

WO (Workshop)

Languages

Freiburg

3 days

May 06, 2024

Info

FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator

Compact VHDL Testbenches and Verification with OSVVM

WO (Workshop)

Languages

Berlin

3 days

Aug 06, 2024

Info

FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator

Compact VHDL Testbenches and Verification with OSVVM

WO (Workshop)

Languages

Munich

3 days

Oct 16, 2024

Info

FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator

Compact VHDL Testbenches and Verification with OSVVM

OL (Online Live)

Languages

Online

3 days

Jun 12, 2024

Info

FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator

Compact VHDL Testbenches and Verification with OSVVM

OL (Online Live)

Languages

Online

3 days

Dec 09, 2024

Info

FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator

UVM Testbench Made Easy

WO (Workshop)

Languages

Munich

2 days

Apr 25, 2024

Info

FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions

UVM Testbench Made Easy

WO (Workshop)

Languages

Berlin

2 days

Jul 25, 2024

Info

FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions

UVM Testbench Made Easy

WO (Workshop)

Languages

Freiburg

2 days

Oct 24, 2024

Info

FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions

UVM Testbench Made Easy

OL (Online Live)

Languages

Online

2 days

Apr 25, 2024

Info

FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions

UVM Testbench Made Easy

OL (Online Live)

Languages

Online

2 days

Jul 25, 2024

Info

FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions

UVM Testbench Made Easy

OL (Online Live)

Languages

Online

2 days

Oct 24, 2024

Info

FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions

SystemVerilog Advanced Verification for FPGA Design

WO (Workshop)

Languages

Munich

3 days

Apr 22, 2024

Info

FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis

SystemVerilog Advanced Verification for FPGA Design

WO (Workshop)

Languages

Berlin

3 days

Jul 22, 2024

Info

FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis

SystemVerilog Advanced Verification for FPGA Design

WO (Workshop)

Languages

Freiburg

3 days

Oct 21, 2024

Info

FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis

SystemVerilog Advanced Verification for FPGA Design

OL (Online Live)

Languages

Online

3 days

Apr 22, 2024

Info

FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis

SystemVerilog Advanced Verification for FPGA Design

OL (Online Live)

Languages

Online

3 days

Jul 22, 2024

Info

FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis

SystemVerilog Advanced Verification for FPGA Design

OL (Online Live)

Languages

Online

3 days

Oct 21, 2024

Info

FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis

Professional VHDL

PW (Power Workshop)

Languages

Munich

5 days

Apr 22, 2024

Info

FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis

Professional VHDL

PW (Power Workshop)

Languages

Freiburg

5 days

Jul 22, 2024

Info

FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis

Professional VHDL

PW (Power Workshop)

Languages

Frankfurt / Main

5 days

Oct 21, 2024

Info

FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis

Professional VHDL

PW (Power Workshop)

Languages

Freiburg

5 days

Dec 02, 2024

Info

FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis

Professional VHDL

OL (Online Live)

Languages

Online

5 days

Apr 22, 2024

Info

FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis

Professional VHDL

OL (Online Live)

Languages

Online

5 days

Oct 21, 2024

Info

FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis

Professional VHDL Testbenches and Verification with OSVVM

PW (Power Workshop)

Languages

Freiburg

5 days

Jun 24, 2024

Info

FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI

Professional VHDL Testbenches and Verification with OSVVM

PW (Power Workshop)

Languages

Freiburg

5 days

Sep 16, 2024

Info

FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI

Professional VHDL Testbenches and Verification with OSVVM

PW (Power Workshop)

Languages

Stuttgart

5 days

Nov 18, 2024

Info

FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI

Professional VHDL Testbenches and Verification with OSVVM

OL (Online Live)

Languages

Online

5 days

Nov 18, 2024

Info

FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI

Professional Python for Embedded

PW (Power Workshop)

Languages

Freiburg

5 days

Jun 24, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Professional Python for Embedded

PW (Power Workshop)

Languages

Frankfurt / Main

5 days

Sep 23, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Professional Python for Embedded

PW (Power Workshop)

Languages

Berlin

5 days

Nov 25, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Professional Python for Embedded

OL (Online Live)

Languages

Online

5 days

Nov 25, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Compact VHDL for Synthesis

WO (Workshop)

Languages

Freiburg

3 days

Mar 18, 2024

Info

FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado

Compact VHDL for Synthesis

WO (Workshop)

Languages

Frankfurt / Main

3 days

Jun 03, 2024

Info

FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado

Compact VHDL for Synthesis

WO (Workshop)

Languages

Stuttgart

3 days

Sep 02, 2024

Info

FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado

Compact VHDL for Synthesis

WO (Workshop)

Languages

Munich

3 days

Nov 04, 2024

Info

FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado

Compact VHDL for Synthesis

OL (Online Live)

Languages

Online

3 days

Apr 15, 2024

Info

FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado

Compact VHDL for Synthesis

OL (Online Live)

Languages

Online

3 days

Aug 12, 2024

Info

FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado

Compact VHDL for Synthesis

OL (Online Live)

Languages

Online

3 days

Nov 25, 2024

Info

FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado

Compact VHDL for Simulation

WO (Workshop)

Languages

Freiburg

2 days

Mar 21, 2024

Info

FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation

Compact VHDL for Simulation

WO (Workshop)

Languages

Frankfurt / Main

2 days

Jun 06, 2024

Info

FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation

Compact VHDL for Simulation

WO (Workshop)

Languages

Stuttgart

2 days

Sep 05, 2024

Info

FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation

Compact VHDL for Simulation

WO (Workshop)

Languages

Munich

2 days

Nov 07, 2024

Info

FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation

Compact VHDL for Simulation

OL (Online Live)

Languages

Online

2 days

Apr 18, 2024

Info

FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation

Compact VHDL for Simulation

OL (Online Live)

Languages

Online

2 days

Aug 15, 2024

Info

FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation

Compact VHDL for Simulation

OL (Online Live)

Languages

Online

2 days

Nov 28, 2024

Info

FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation

Compact Python for Embedded

WO (Workshop)

Languages

Freiburg

3 days

Jun 24, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Compact Python for Embedded

WO (Workshop)

Languages

Frankfurt / Main

3 days

Sep 23, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Compact Python for Embedded

WO (Workshop)

Languages

Berlin

3 days

Nov 25, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Compact Python for Embedded

OL (Online Live)

Languages

Online

3 days

Nov 25, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

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How can we help?

Contact

FAQ

01. Can you help me with reserving the room?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

02. What times in the day do courses start and end?

Our face-to-face courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours. For online courses, the start is also at 9 a.m. (CET/CEST), but they end at 2:30 p.m.. The total course time per day is 4 and a half hours plus breaks.

03. Are course materials provided?

All participants of paid courses will receive English training materials in electronic or paper form.

04. Will I receive a course certificate?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

05. Can I pay with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

06. What are the options for payment?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

07. What is the deadline for payment?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

08. What are the options for cancelling?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

09. When will I receive a firm commitment as to whether the course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

10. How many participants are required for a course to be given/what is the minimum number of participants?

We generally offer courses for 5 or more people. That means that if you would like to book a course at your premises, you need 5 people to register or need to pay the amount for 5 participants, even if fewer people attend.

11. Can I book a course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

12. What language is the course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.