PLC2 Training

Programming Languages

Familiarize yourself with the latest design methods to get the most out of your chosen technology. Learn the fundamentals and become an expert in HDL languages such as VHDL or System Verilog.
We offer a variety of workshops and training sessions to introduce you to System Verilog, HDL, and VHDL. You will learn the VHDL synthesis and simulation concept and understand how to use different synthesis or simulation constructs to design your FPGA.

Upcoming Trainings

Course	Format	Category	Location	Duration	Date
VHDL Circuit Simulation Part 2: Stimulus Generation and Behavior Verification	WE (Webinar)	Programming Languages	Online	1 hour	on demand	Info VHDL circuit simulation simulations FPGA AMD webinar
VHDL Circuit Simulation Part 1: Behavior Modeling, Timing, and File I/O	WE (Webinar)	Programming Languages	Online	1 hour	on demand	Info VHDL circuit simulation simulations FPGA AMD webinar
VHDL Circuit Design Part 2: Advanced Concepts and Behavioral Modeling	WE (Webinar)	Programming Languages	Online	1 hour	on demand	Info VHDL circuit design designs application applications behavioral modeling AMD webinar
VHDL Circuit Design Part 1: Fundamentals and Methodologies	WE (Webinar)	Programming Languages	Online	1 hour	on demand	Info VHDL circuit design designs application applications AMD webinar HDL hardware design
Circuit Synthesis with VHDL	SE (Seminar)	Programming Languages	Frankfurt / Main	1 day	Apr 03, 2025	Info FPGA HDL VHDL HDL Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream
Circuit Synthesis with VHDL	SE (Seminar)	Programming Languages	Stuttgart	1 day	Oct 01, 2025	Info FPGA HDL VHDL HDL Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream
Circuit Simulation with VHDL	SE (Seminar)	Programming Languages	Freiburg	1 day	May 27, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation
Circuit Simulation with VHDL	SE (Seminar)	Programming Languages	Frankfurt / Main	1 day	Nov 12, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation
Compact SystemVerilog for Synthesis	WO (Workshop)	Programming Languages	Stuttgart	3 days	Feb 03, 2025	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact SystemVerilog for Synthesis	WO (Workshop)	Programming Languages	Frankfurt / Main	3 days	Apr 22, 2025	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact SystemVerilog for Synthesis	WO (Workshop)	Programming Languages	Freiburg	3 days	Jul 28, 2025	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact SystemVerilog for Synthesis	WO (Workshop)	Programming Languages	Munich	3 days	Oct 29, 2025	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact SystemVerilog for Synthesis	OL (Online Live)	Programming Languages	Online	3 days	Feb 03, 2025	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact SystemVerilog for Synthesis	OL (Online Live)	Programming Languages	Online	3 days	Apr 22, 2025	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact SystemVerilog for Synthesis	OL (Online Live)	Programming Languages	Online	3 days	Jul 28, 2025	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact SystemVerilog for Synthesis	OL (Online Live)	Programming Languages	Online	3 days	Oct 29, 2025	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact Verilog	WO (Workshop)	Programming Languages		3 days	all year on request	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact Verilog	OL (Online Live)	Programming Languages		3 days	all year on request	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Advanced VHDL	WO (Workshop)	Programming Languages	Stuttgart	3 days	Mar 24, 2025	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL	WO (Workshop)	Programming Languages	Frankfurt / Main	3 days	Jul 21, 2025	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL	WO (Workshop)	Programming Languages	Freiburg	3 days	Oct 29, 2025	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL	WO (Workshop)	Programming Languages	Munich	3 days	Dec 15, 2025	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL	OL (Online Live)	Programming Languages	Online	3 days	Mar 24, 2025	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL	OL (Online Live)	Programming Languages	Online	3 days	Jul 21, 2025	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL	OL (Online Live)	Programming Languages	Online	3 days	Oct 29, 2025	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL	OL (Online Live)	Programming Languages	Online	3 days	Dec 15, 2025	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Compact VHDL Testbenches and Verification with OSVVM	WO (Workshop)	Programming Languages	Stuttgart	3 days	Mar 04, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Compact VHDL Testbenches and Verification with OSVVM	WO (Workshop)	Programming Languages	Freiburg	3 days	May 26, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Compact VHDL Testbenches and Verification with OSVVM	WO (Workshop)	Programming Languages	Berlin	3 days	Aug 05, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Compact VHDL Testbenches and Verification with OSVVM	WO (Workshop)	Programming Languages	Munich	3 days	Oct 06, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Compact VHDL Testbenches and Verification with OSVVM	OL (Online Live)	Programming Languages	Online	3 days	Mar 04, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Compact VHDL Testbenches and Verification with OSVVM	OL (Online Live)	Programming Languages	Online	3 days	May 26, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Compact VHDL Testbenches and Verification with OSVVM	OL (Online Live)	Programming Languages	Online	3 days	Aug 05, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Compact VHDL Testbenches and Verification with OSVVM	OL (Online Live)	Programming Languages	Online	3 days	Oct 06, 2025	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
UVM Testbench Made Easy	WO (Workshop)	Programming Languages		2 days	all year on request	Info FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions
UVM Testbench Made Easy	OL (Online Live)	Programming Languages		2 days	all year on request	Info FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions
SystemVerilog Advanced Verification for FPGA Design	WO (Workshop)	Programming Languages		3 days	all year on request	Info FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis
SystemVerilog Advanced Verification for FPGA Design	OL (Online Live)	Programming Languages		3 days	all year on request	Info FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis
Professional VHDL	PW (Power Workshop)	Programming Languages	Freiburg	5 days	Feb 24, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	PW (Power Workshop)	Programming Languages	Munich	5 days	May 05, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	PW (Power Workshop)	Programming Languages	Freiburg	5 days	Jul 21, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	PW (Power Workshop)	Programming Languages	Frankfurt / Main	5 days	Oct 06, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	PW (Power Workshop)	Programming Languages	Freiburg	5 days	Dec 15, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	OL (Online Live)	Programming Languages	Online	5 days	Feb 24, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	OL (Online Live)	Programming Languages	Online	5 days	May 05, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	OL (Online Live)	Programming Languages	Online	5 days	Jul 21, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	OL (Online Live)	Programming Languages	Online	5 days	Oct 06, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	OL (Online Live)	Programming Languages	Online	5 days	Dec 15, 2025	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL Testbenches and Verification with OSVVM	PW (Power Workshop)	Programming Languages	Frankfurt / Main	5 days	Feb 10, 2025	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional VHDL Testbenches and Verification with OSVVM	PW (Power Workshop)	Programming Languages	Freiburg	5 days	Jun 23, 2025	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional VHDL Testbenches and Verification with OSVVM	PW (Power Workshop)	Programming Languages	Freiburg	5 days	Sep 08, 2025	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional VHDL Testbenches and Verification with OSVVM	PW (Power Workshop)	Programming Languages	Stuttgart	5 days	Nov 17, 2025	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional VHDL Testbenches and Verification with OSVVM	OL (Online Live)	Programming Languages	Online	5 days	Feb 10, 2025	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional VHDL Testbenches and Verification with OSVVM	OL (Online Live)	Programming Languages	Online	5 days	Jun 23, 2025	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional VHDL Testbenches and Verification with OSVVM	OL (Online Live)	Programming Languages	Online	5 days	Sep 08, 2025	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional VHDL Testbenches and Verification with OSVVM	OL (Online Live)	Programming Languages	Online	5 days	Nov 17, 2025	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional Python for Embedded	PW (Power Workshop)	Programming Languages	Stuttgart	5 days	Mar 24, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Professional Python for Embedded	PW (Power Workshop)	Programming Languages	Freiburg	5 days	Jun 02, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Professional Python for Embedded	PW (Power Workshop)	Programming Languages	Frankfurt / Main	5 days	Sep 22, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Professional Python for Embedded	PW (Power Workshop)	Programming Languages	Berlin	5 days	Nov 24, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Professional Python for Embedded	OL (Online Live)	Programming Languages	Online	5 days	Mar 24, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Professional Python for Embedded	OL (Online Live)	Programming Languages	Online	5 days	Jun 02, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Professional Python for Embedded	OL (Online Live)	Programming Languages	Online	5 days	Sep 22, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Professional Python for Embedded	OL (Online Live)	Programming Languages	Online	5 days	Nov 24, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact VHDL for Synthesis	WO (Workshop)	Programming Languages	Berlin	3 days	Jan 27, 2025	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Synthesis	WO (Workshop)	Programming Languages	Freiburg	3 days	Mar 17, 2025	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Synthesis	WO (Workshop)	Programming Languages	Frankfurt / Main	3 days	Jun 02, 2025	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Synthesis	WO (Workshop)	Programming Languages	Stuttgart	3 days	Sep 15, 2025	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Synthesis	WO (Workshop)	Programming Languages	Munich	3 days	Nov 03, 2025	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Synthesis	OL (Online Live)	Programming Languages	Online	3 days	Jan 27, 2025	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Synthesis	OL (Online Live)	Programming Languages	Online	3 days	Mar 17, 2025	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Synthesis	OL (Online Live)	Programming Languages	Online	3 days	Jun 02, 2025	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Synthesis	OL (Online Live)	Programming Languages	Online	3 days	Sep 15, 2025	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Synthesis	OL (Online Live)	Programming Languages	Online	3 days	Nov 03, 2025	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Simulation	WO (Workshop)	Programming Languages	Berlin	2 days	Jan 30, 2025	Info FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation
Compact VHDL for Simulation	WO (Workshop)	Programming Languages	Freiburg	2 days	Mar 20, 2025	Info FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation
Compact VHDL for Simulation	WO (Workshop)	Programming Languages	Frankfurt / Main	2 days	Jun 05, 2025	Info FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation
Compact VHDL for Simulation	WO (Workshop)	Programming Languages	Stuttgart	2 days	Sep 18, 2025	Info FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation
Compact VHDL for Simulation	WO (Workshop)	Programming Languages	Munich	2 days	Nov 06, 2025	Info FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation
Compact VHDL for Simulation	OL (Online Live)	Programming Languages	Online	2 days	Jan 30, 2025	Info FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation
Compact VHDL for Simulation	OL (Online Live)	Programming Languages	Online	2 days	Mar 20, 2025	Info FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation
Compact VHDL for Simulation	OL (Online Live)	Programming Languages	Online	2 days	Jun 05, 2025	Info FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation
Compact VHDL for Simulation	OL (Online Live)	Programming Languages	Online	2 days	Sep 18, 2025	Info FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation
Compact VHDL for Simulation	OL (Online Live)	Programming Languages	Online	2 days	Nov 06, 2025	Info FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation
Compact Python for Embedded	WO (Workshop)	Programming Languages	Stuttgart	3 days	Mar 24, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact Python for Embedded	WO (Workshop)	Programming Languages	Freiburg	3 days	Jun 02, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact Python for Embedded	WO (Workshop)	Programming Languages	Frankfurt / Main	3 days	Sep 22, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact Python for Embedded	WO (Workshop)	Programming Languages	Berlin	3 days	Nov 24, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact Python for Embedded	OL (Online Live)	Programming Languages	Online	3 days	Mar 24, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact Python for Embedded	OL (Online Live)	Programming Languages	Online	3 days	Jun 02, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact Python for Embedded	OL (Online Live)	Programming Languages	Online	3 days	Sep 22, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact Python for Embedded	OL (Online Live)	Programming Languages	Online	3 days	Nov 24, 2025	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
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Training Formats

Online Live

Online course
In-depth exercises in real-time
Remote access on utilized software and hardware

EXPLORE

Webinar

Good overview of a topic
Technical focus
Online

EXPLORE

Seminar

1-day technical deep dive
Free of charge
For developers, department heads, and managers

EXPLORE

Easy Start

Perfect for beginners and project managers
With a focus on practical exercises

EXPLORE

Workshop

Compact 1- to 3-day workshop
Ideal for developers
Theory and practice

EXPLORE

Power Workshop

5-day power workshop
Very extensive further training
Practice-oriented on PC and evaluation board
Detailed treatment of technical topics

EXPLORE

Long Term Education

3 months training
For engineers and technicians
Including comprehensive training material

EXPLORE

More PLC2 Training
Categories

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

In today’s competitive world of electronic engineering the difference is made at the system architectural level. Making the right choices at the start of your design makes the difference between mediocre versus excellent results.

Learn more

Development
Tools & Methodology

The HDL based development method simplifies the development cycle, but this requires the developer to have good knowledge of digital circuit design.

Learn more

Embedded for AMD (Adaptive) SoCs & MPSoCs

Are you a beginner in the embedded world or a very experienced embedded developer, we at PLC2 tailor our embedded classes to your level. Our workshops include everything you need to know on how to develop embedded solutions with AMD's wide range of SoCs.

Learn more

DSP & Image Processing

With their inherent flexibility, AMD FPGAs and SoCs are ideal for high-performance or multi-channel digital signal processing (DSP) applications that can take advantage of hardware parallelism.

Learn more

Connectivity

How do you keep up with the edge network emerging applications that are redefining hardware requirements for electronic designers? Are you designing the next generation AI for IoT, embedded vision, hardware security, 5G communication or industrial/automotive automation for your company?

Learn more

How can we help?

Contact

Call PLC2

+49 7664 91313-15

Send an e-mail

michael.schwarz@plc2.de

FAQ

01. Can you help me with reserving the room?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

02. What times in the day do courses start and end?

Our face-to-face and online courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours.

03. Are course materials provided?

All participants of paid courses will receive English training materials in electronic or paper form.

04. Will I receive a course certificate?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

05. Can I pay with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

06. What are the options for payment?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

07. What is the deadline for payment?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

08. What are the options for cancelling?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

09. When will I receive a firm commitment as to whether the course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

10. How many participants are required for a course to be given/what is the minimum number of participants?

We generally offer courses for 5 or more people. That means that if you would like to book a course at your premises, you need 5 people to register or need to pay the amount for 5 participants, even if fewer people attend.

11. Can I book a course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

12. What language is the course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.