Compact SystemVerilog for Synthesis
The continuously rising demand for highly complex programmable logic in combination with ever-increasing clock rates hold challenges for the users. SystemVerilog (IEEE 1800) as the successor of the already very popular Verilog Hardware Description Language (HDL) brings all features to describe logic in a scalable and reusable fashion, extending the design methods seamlessly into verification. It has become a major tool of choice in FGPA and ASIC designs, supported by virtually all EDA vendor tools.
In this workshop, SystemVerilog is presented using a set of modern and powerful HDL-based design techniques that support a high design quality for any physical target. The examples and labs during the sessions aim at FPGA fabric as a demonstration vehicle for language features, while SystemVerilog is even more established in ASIC designs. The course presents the SystemVerilog concepts and core syntax and fosters insight into its successful usage. Also, attendees are introduced to basic modular design elements as well as principal verification approaches set within the hardware programming language.
All theoretical topics are complemented with PC-based exercises in synthesis and simulation. Within these exercises, the attendees will create multiple SystemVerilog modules that constitute a larger design context. The development cycle will be closed by implementing and - for the face-to-face attendees - porting such a design onto an FPGA evaluation board, allowing you to gain insight into device configuration and observability of an operational design. Attendees of the online live training will perform the practical exercises in real time with instructor assistance.
The extended SystemVerilog features for verification are not covered in this agenda. To gain insight into these language features, please review the workshop »SystemVerilog Advanced Verification for FPGA Design« or consult PLC2 Training.
Course language: English
Contact
Michael Schwarz
+49 7664 91313-15
Details
Applicable technologies
Generic, AMD FPGAs and adaptive SoCsRequirements
Basic knowledge of digital technologyDuration
3 daysFee (net per person)
€ 1,900Inclusive
Training materialAgenda
01
Introduction
02
SystemVerilog concepts
Keywords
03
Data types
Net and variable data types
04
Aggregate types
Arrays and strings
User defined types and type casting
05
Operators
06
Data flow modeling
Continuous assignments
Blocking assignments
07
Procedural statements
08
Control flow statements
09
Functions and tasks
10
Hierarchy constructs
Module and packages
Generate statements
Interfaces
11
Introduction to FSM design
12
Testbenches
File I/O
13
Application Programming Interfaces (API)
DPI, PLI/VPI
14
Targeting AMD FPGAs
Dates
Compact SystemVerilog for Synthesis
OL
Online
Feb 03, 2025
Compact SystemVerilog for Synthesis
OL
Online
Apr 22, 2025
Compact SystemVerilog for Synthesis
OL
Online
Jul 28, 2025
Compact SystemVerilog for Synthesis
OL
Online
Oct 29, 2025
Available formats for this training
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