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Compact SystemVerilog for Synthesis

Workshop


Online Live

The continuously rising demand for highly complex programmable logic in combination with ever-increasing clock rates hold challenges for the users. SystemVerilog (IEEE 1800) as the successor of the already very popular Verilog Hardware Description Language (HDL) brings all features to describe logic in a scalable and reusable fashion, extending the design methods seamlessly into verification. It has become a major tool of choice in FGPA and ASIC designs, supported by virtually all EDA vendor tools.

In this workshop, SystemVerilog is presented using a set of modern and powerful HDL-based design techniques that support a high design quality for any physical target. The examples and labs during the sessions aim at FPGA fabric as a demonstration vehicle for language features, while SystemVerilog is even more established in ASIC designs. The course presents the SystemVerilog concepts and core syntax and fosters insight into its successful usage. Also, attendees are introduced to basic modular design elements as well as principal verification approaches set within the hardware programming language.

All theoretical topics are complemented with PC-based exercises in synthesis and simulation. Within these exercises, the attendees will create multiple SystemVerilog modules that constitute a larger design context. The development cycle will be closed by implementing and - for the face-to-face attendees - porting such a design onto an FPGA evaluation board, allowing you to gain insight into device configuration and observability of an operational design.

The extended SystemVerilog features for verification are not covered in this agenda. To gain insight into these language features, please review the workshop »SystemVerilog Advanced Verification for FPGA Design« or consult PLC2 Training.

Course language: German (English possible on request)

Portrait von Michael Schwarz

Contact

Michael Schwarz

+49 7664 91313-15

michael.schwarz@plc2.de

Details

Applicable technologies

Generic, AMD FPGAs and adaptive SoCs

Requirements

Basic knowledge of digital technology

Duration

3 days

Fee (net per person)

€ 2,300

Inclusive

Training material
Plus beverages during breaks
Lunch

Agenda

01

Introduction

02

SystemVerilog concepts

Keywords

03

Data types

Net and variable data types

04

Aggregate types

Arrays and strings
User defined types and type casting

05

Operators

06

Data flow modeling

Continuous assignments
Blocking assignments

07

Procedural statements

08

Control flow statements

09

Functions and tasks

10

Hierarchy constructs

Module and packages
Generate statements
Interfaces

11

Introduction to FSM design

12

Testbenches

File I/O

13

Application Programming Interfaces (API)

DPI, PLI/VPI

14

Targeting AMD FPGAs

Dates

Compact SystemVerilog for Synthesis

WO

Freiburg

Jul 10, 2024

Book now

Compact SystemVerilog for Synthesis

WO

Munich

Oct 07, 2024

Book now

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€ 2,300

Course

Compact SystemVerilog for Synthesis_WO

Total fee

€ 2,300

*Required field

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Kosten

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€ 2,300

Kurs

Compact SystemVerilog for Synthesis_WO

Gesamtbetrag

€ 2,300

*Pflichtfeld

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Contact

FAQ

01. Can you help me with reserving the room?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

02. What times in the day do courses start and end?

Our face-to-face courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours. For online courses, the start is also at 9 a.m. (CET/CEST), but they end at 2:30 p.m.. The total course time per day is 4 and a half hours plus breaks.

03. Are course materials provided?

All participants of paid courses will receive English training materials in electronic or paper form.

04. Will I receive a course certificate?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

05. Can I pay with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

06. What are the options for payment?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

07. What is the deadline for payment?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

08. What are the options for cancelling?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

09. When will I receive a firm commitment as to whether the course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

10. How many participants are required for a course to be given/what is the minimum number of participants?

We generally offer courses for 5 or more people. That means that if you would like to book a course at your premises, you need 5 people to register or need to pay the amount for 5 participants, even if fewer people attend.

11. Can I book a course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

12. What language is the course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.