PLC2 Training

Development
Tools & Methodology

The HDL based development method simplifies the development cycle, but this requires the developer to have good knowledge of digital circuit design. It is not enough to know how to implement combinational and sequential circuits, it is very important to know how to implement your design in the FPGA architecture to maximize benefits in size, power and performance.
The PLC2 training courses in the »tools and methodology« category help developers use and apply the development tools for these latest technologies.

Upcoming Trainings

Course	Format	Category	Location	Duration	Date
FPGA Timing Constraints: A Comprehensive Overview	WE (Webinar)	Development Tools & Methodology	Online	1 hour	on demand	Info FPGA timing constraints AMD Vivado AMD FPGA design flow virtual clocks webinar
Multimedia Accelerators for Kria SoM with HLS & Vitis Libraries	WE (Webinar)	Development Tools & Methodology	Online	1 hour	on demand	Info
Vitis Tools for Acceleration - Creating a RTL Kernel: From HDL to Reusable Packaged Kernel	WE (Webinar)	Development Tools & Methodology	Online	1 hour	on demand	Info Vitis, RTL kernel, acceleration, design flow
Vitis - Huge Debugging Varieties	WE (Webinar)	Development Tools & Methodology	Online	1 hour	on demand	Info Versal, AI, webinar, framework, debugger
Vitis AI - Creating an Edge Inference Solution - FPGA-Based Deep Learning (DNN) Accelerator	WE (Webinar)	Development Tools & Methodology	Online	1 hour	on demand	Info
Vitis AI - Whole Application Acceleration Using Versal VCK190	WE (Webinar)	Development Tools & Methodology	Online	1 hour	on demand	Info
Advanced Vivado	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Jul 10, 2024	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	Oct 28, 2024	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado	OL (Online Live)	Development Tools & Methodology	Online	3 days	Jul 10, 2024	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado	OL (Online Live)	Development Tools & Methodology	Online	3 days	Oct 28, 2024	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
FPGA Designer (Long Term)	LT (Long Term Education)	Development Tools & Methodology	Freiburg	8 dates of 2 days each	Sep 10, 2024	Info
Compact Vivado Design Suite Tool Flow	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	2 days	Jun 03, 2024	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
Compact Vivado Design Suite Tool Flow	WO (Workshop)	Development Tools & Methodology	Stuttgart	2 days	Sep 16, 2024	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
Compact Vivado Design Suite Tool Flow	WO (Workshop)	Development Tools & Methodology	Munich	2 days	Nov 04, 2024	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
Compact Vivado Design Suite Tool Flow	OL (Online Live)	Development Tools & Methodology	Online	2 days	Jul 22, 2024	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
Compact Vivado Design Suite Tool Flow	OL (Online Live)	Development Tools & Methodology	Online	2 days	Oct 07, 2024	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
Compact Timing Constraints and Analysis	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	Jun 05, 2024	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Sep 18, 2024	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis	WO (Workshop)	Development Tools & Methodology	Munich	3 days	Nov 06, 2024	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis	OL (Online Live)	Development Tools & Methodology	Online	3 days	Jul 24, 2024	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis	OL (Online Live)	Development Tools & Methodology	Online	3 days	Oct 09, 2024	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
FPGA Circuit Design Technique	SE (Seminar)	Development Tools & Methodology	Freiburg	1 day	Sep 25, 2024	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung IP Core
Professional Vivado	PW (Power Workshop)	Development Tools & Methodology	Frankfurt / Main	5 days	Jul 22, 2024	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Oct 07, 2024	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	PW (Power Workshop)	Development Tools & Methodology	Frankfurt / Main	5 days	Dec 09, 2024	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	OL (Online Live)	Development Tools & Methodology	Online	5 days	Jul 22, 2024	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	OL (Online Live)	Development Tools & Methodology	Online	5 days	Oct 07, 2024	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vitis	PW (Power Workshop)	Development Tools & Methodology	Stuttgart	5 days	Jun 24, 2024	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT
Professional Vitis	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Aug 05, 2024	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT
Professional Vitis	PW (Power Workshop)	Development Tools & Methodology	Berlin	5 days	Nov 04, 2024	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT
Professional Vitis	OL (Online Live)	Development Tools & Methodology	Online	5 days	Nov 04, 2024	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT
Professional FPGA Circuit Design Technique	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Jul 15, 2024	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Nov 04, 2024	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique	OL (Online Live)	Development Tools & Methodology	Online	5 days	Nov 04, 2024	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Git for EDA Tool Flows	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	Jun 10, 2024	Info Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging
Git for EDA Tool Flows	WO (Workshop)	Development Tools & Methodology	Munich	3 days	Sep 09, 2024	Info Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging
Git for EDA Tool Flows	WO (Workshop)	Development Tools & Methodology	Freiburg	3 days	Dec 16, 2024	Info Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging
Git for EDA Tool Flows	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 11, 2024	Info Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging
FPGA Power Optimization	WO (Workshop)	Development Tools & Methodology		2 days	all year on request	Info FPGA Power Vivado Kintex XCE clocking
FPGA Power Optimization	OL (Online Live)	Development Tools & Methodology		2 days	all year on request	Info FPGA Power Vivado Kintex XCE clocking
Easy Start FPGA Vivado	ES (Easy Start)	Development Tools & Methodology	Munich	2 days	May 27, 2024	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Easy Start FPGA Vivado	ES (Easy Start)	Development Tools & Methodology	Stuttgart	2 days	Aug 08, 2024	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Easy Start FPGA Vivado	ES (Easy Start)	Development Tools & Methodology	Frankfurt / Main	2 days	Nov 14, 2024	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Easy Start FPGA Vivado	OL (Online Live)	Development Tools & Methodology	Online	2 days	Jul 29, 2024	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Easy Start FPGA Vivado	OL (Online Live)	Development Tools & Methodology	Online	2 days	Dec 04, 2024	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Dynamic Function eXchange (DFX)	WO (Workshop)	Development Tools & Methodology	Stuttgart	2 days	Jul 08, 2024	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Dynamic Function eXchange (DFX)	WO (Workshop)	Development Tools & Methodology	Freiburg	2 days	Oct 01, 2024	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Dynamic Function eXchange (DFX)	OL (Online Live)	Development Tools & Methodology	Online	2 days	Oct 01, 2024	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Designing with the Xilinx Analog Mixed Signal Solution	WO (Workshop)	Development Tools & Methodology		2 days	all year on request	Info FPGA AMS Vivado XADC DAC
Designing with the Xilinx Analog Mixed Signal Solution	OL (Online Live)	Development Tools & Methodology		2 days	all year on request	Info FPGA AMS Vivado XADC DAC
Debugging Techniques Using the Vivado Logic Analyzer	WO (Workshop)	Development Tools & Methodology	Freiburg	2 days	Jun 26, 2024	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Debugging Techniques Using the Vivado Logic Analyzer	WO (Workshop)	Development Tools & Methodology	Stuttgart	2 days	Sep 12, 2024	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Debugging Techniques Using the Vivado Logic Analyzer	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	2 days	Dec 02, 2024	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Debugging Techniques Using the Vivado Logic Analyzer	OL (Online Live)	Development Tools & Methodology	Online	2 days	Jun 26, 2024	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Debugging Techniques Using the Vivado Logic Analyzer	OL (Online Live)	Development Tools & Methodology	Online	2 days	Dec 02, 2024	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Continuous Integration for EDA Tools	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	May 13, 2024	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Continuous Integration for EDA Tools	PW (Power Workshop)	Development Tools & Methodology	Frankfurt / Main	5 days	Jul 08, 2024	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Continuous Integration for EDA Tools	PW (Power Workshop)	Development Tools & Methodology	Berlin	5 days	Oct 07, 2024	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Continuous Integration for EDA Tools	OL (Online Live)	Development Tools & Methodology	Online	5 days	May 13, 2024	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Continuous Integration for EDA Tools	OL (Online Live)	Development Tools & Methodology	Online	5 days	Oct 14, 2024	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Compact Vitis for the Software Designer	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	May 22, 2024	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
Compact Vitis for the Software Designer	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	Sep 17, 2024	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
Compact Vitis for the Software Designer	WO (Workshop)	Development Tools & Methodology	Munich	3 days	Dec 16, 2024	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
Compact Vitis for the Software Designer	OL (Online Live)	Development Tools & Methodology	Online	3 days	Dec 16, 2024	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
Compact Vitis for Acceleration	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	May 27, 2024	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging
Compact Vitis for Acceleration	WO (Workshop)	Development Tools & Methodology	Freiburg	3 days	Aug 12, 2024	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging
Compact Vitis for Acceleration	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	Nov 20, 2024	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging
Compact Vitis for Acceleration	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 20, 2024	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging
Compact Vitis AI	WO (Workshop)	Development Tools & Methodology	Freiburg	3 days	Jun 10, 2024	Info Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software
Compact Vitis AI	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Sep 23, 2024	Info Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software
Compact Vitis AI	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	Nov 04, 2024	Info Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software
Compact Vitis AI	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 04, 2024	Info Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software
Compact FPGA Circuit Design Technique	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	May 22, 2024	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Compact FPGA Circuit Design Technique	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Aug 05, 2024	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Compact FPGA Circuit Design Technique	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	Oct 09, 2024	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Compact FPGA Circuit Design Technique	OL (Online Live)	Development Tools & Methodology	Online	3 days	Jun 10, 2024	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Compact FPGA Circuit Design Technique	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 16, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Compact FPGA Circuit Design Technique	OL (Online Live)	Development Tools & Methodology	Online	3 days	Dec 09, 2024	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
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Training Formats

Online Live

Online course
In-depth exercises in self-study

EXPLORE

Webinar

Good overview of a topic
Technical focus
Online

EXPLORE

Seminar

1-day technical deep dive
Free of charge
For developers, department heads, and managers

EXPLORE

Easy Start

Perfect for beginners and project managers
With a focus on practical exercises

EXPLORE

Workshop

Compact 2- or 3-day workshop
Ideal for developers
Theory and practice

EXPLORE

Power Workshop

4 or 5 days
Very extensive further training
Practice-oriented on PC and evaluation board
Detailed treatment of technical topics

EXPLORE

Long Term Education

3 months training
For engineers and technicians
Including comprehensive training material

EXPLORE

More PLC2 Training
Categories

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

In today’s competitive world of electronic engineering the difference is made at the system architectural level. Making the right choices at the start of your design makes the difference between mediocre versus excellent results.

Learn more

Programming Languages

Familiarize yourself with the latest design methods to get the most out of your chosen technology. Learn the fundamentals and become an expert in HDL languages such as VHDL or System Verilog.

Learn more

Embedded for AMD (Adaptive) SoCs & MPSoCs

Are you a beginner in the embedded world or a very experienced embedded developer, we at PLC2 tailor our embedded classes to your level. Our workshops include everything you need to know on how to develop embedded solutions with AMD's wide range of SoCs.

Learn more

DSP & Image Processing

With their inherent flexibility, AMD FPGAs and SoCs are ideal for high-performance or multi-channel digital signal processing (DSP) applications that can take advantage of hardware parallelism.

Learn more

Connectivity

How do you keep up with the edge network emerging applications that are redefining hardware requirements for electronic designers? Are you designing the next generation AI for IoT, embedded vision, hardware security, 5G communication or industrial/automotive automation for your company?

Learn more

How can we help?

Contact

Call PLC2

+49 7664 91313-15

Send an e-mail

michael.schwarz@plc2.de

FAQ

01. Can you help me with reserving the room?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

02. What times in the day do courses start and end?

Our face-to-face courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours. For online courses, the start is also at 9 a.m. (CET/CEST), but they end at 2:30 p.m.. The total course time per day is 4 and a half hours plus breaks.

03. Are course materials provided?

All participants of paid courses will receive English training materials in electronic or paper form.

04. Will I receive a course certificate?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

05. Can I pay with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

06. What are the options for payment?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

07. What is the deadline for payment?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

08. What are the options for cancelling?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

09. When will I receive a firm commitment as to whether the course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

10. How many participants are required for a course to be given/what is the minimum number of participants?

We generally offer courses for 5 or more people. That means that if you would like to book a course at your premises, you need 5 people to register or need to pay the amount for 5 participants, even if fewer people attend.

11. Can I book a course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

12. What language is the course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.

Development Tools & Methodology

Upcoming Trainings

Development
Tools & Methodology