Menu

PLC2 Training Format

Specialized Workshops for FPGA/MPSoC Developers on All Levels

As the world's first and long-standing Authorized Training Provider of AMD Xilinx (ATP), we always have access to brand-new technologies, methods, and development tools and work on the technological pulse of the times.
In our two- and three-day workshops, we share our knowledge with developers and train them in technical depth. During the training, the participant has the chance to consolidate and reinforce the knowledge imparted by our experts in practical exercises. The training portfolio ranges from workshops covering all HDL users to specific AMD Xilinx technology training. The content focuses on methodologies for development and verification, the architecture of the latest building blocks, physical implementation, and the application of the highly complex development tools.

Workshop in a Nutshell

Be the first to learn from the experts

As an Authorized Training Provider PLC2 is the first to have access to the latest AMD Xilinx technologies, design methods, and tools.
01

Compact two or three days workshop

During this workshop we will share our knowledge with developers and provide them with deep technical training on the selected topic.
02

Solid mix of technical and practical class

During the workshop our experts will reinforce the learned knowledge into practical exercises.
03

Wide range of portfolio

From HDL users to AMD Xilinx latest and most popular technology training with content ranging from methodologies, architectures, physical implementations, and applications.
04

Upcoming Workshops

Course Format Category Location Duration Date

Compact SystemVerilog for Synthesis

WO (Workshop)

Programming Languages

Freiburg

3 days

Jul 10, 2024

Info

FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis

Compact SystemVerilog for Synthesis

WO (Workshop)

Programming Languages

Munich

3 days

Oct 07, 2024

Info

FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis

Compact Verilog

WO (Workshop)

Programming Languages

3 days

all year on request

Info

FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis

Advanced VHDL

WO (Workshop)

Programming Languages

Frankfurt / Main

3 days

Jul 15, 2024

Info

Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool

Advanced VHDL

WO (Workshop)

Programming Languages

Freiburg

3 days

Oct 28, 2024

Info

Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool

Advanced VHDL

WO (Workshop)

Programming Languages

Munich

3 days

Dec 09, 2024

Info

Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool

Compact MicroBlaze System Design

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

3 days

all year on request

Info

Embedded MicroBlaze System Design Systems FPGA hardware software AMD tool tools custom peripheral application debugging integration microprocessor microprocessors Vivado Vitis

Compact VHDL Testbenches and Verification with OSVVM

WO (Workshop)

Programming Languages

Berlin

3 days

Aug 06, 2024

Info

FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator

Compact VHDL Testbenches and Verification with OSVVM

WO (Workshop)

Programming Languages

Munich

3 days

Oct 16, 2024

Info

FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator

Advanced Vivado

WO (Workshop)

Development
Tools & Methodology

Stuttgart

3 days

Jul 10, 2024

Info

Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog

Advanced Vivado

WO (Workshop)

Development
Tools & Methodology

Frankfurt / Main

3 days

Oct 28, 2024

Info

Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog

Compact Versal Adaptive SoC: PCI Express Systems

WO (Workshop)

Connectivity

Stuttgart

2 days

Oct 14, 2024

Info

Versal PCI Express Integrated Block for PCI Express Gen4 PL PCIe CPM PCIe High-Speed Interfaces Transceiver DDR4 PCB Design PCB Simulation ACAP PCIe endpoint root port DMA VCK190

Compact Zynq 7000 SoC for the Software Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

3 days

all year on request

Info

Embedded Architecture Vivado Vitis SoC Cortex-A9 Processor Cache PetaLinux Linux PS AXI

Embedded Linux Driver Development

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

3 days

Aug 05, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Driver Character Yocto tool flow Zynq

Embedded Linux Driver Development

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

3 days

Oct 16, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Driver Character Yocto tool flow Zynq

Embedded Design with PetaLinux Tools

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

2 days

Jun 26, 2024

Info

Embedded Linux PetaLinux build rootfs kernel driver layer DeviceTree Device-Tree Boot

Embedded Design with PetaLinux Tools

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

2 days

Sep 11, 2024

Info

Embedded Linux PetaLinux build rootfs kernel driver layer DeviceTree Device-Tree Boot

Embedded Design with PetaLinux Tools

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Munich

2 days

Nov 28, 2024

Info

Embedded Linux PetaLinux build rootfs kernel driver layer DeviceTree Device-Tree Boot

Developing Multimedia Solutions with the VCU and GStreamer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

2 days

Jul 29, 2024

Info

SoM Vision Video streaming data application codec Kria Embedded Multimedia Gstreamer VCU Camera PetaLinux Linux Kernel

Developing Multimedia Solutions with the VCU and GStreamer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

2 days

Oct 17, 2024

Info

SoM Vision Video streaming data application codec Kria Embedded Multimedia Gstreamer VCU Camera PetaLinux Linux Kernel

Compact Zynq 7000 SoC for the Hardware Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

3 days

all year on request

Info

Embedded Architecture Vivado Vitis Zynq SoC Platform Hardware C AXI

Compact Zynq UltraScale+ MPSoC for the Software Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

3 days

Aug 06, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Compact Zynq UltraScale+ MPSoC for the Software Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

3 days

Nov 18, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Compact Zynq UltraScale+ MPSoC for the Hardware Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

3 days

Aug 20, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE

Compact Zynq UltraScale+ MPSoC for the Hardware Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Munich

3 days

Nov 25, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE

Compact Versal Adaptive SoC for the Software Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

3 days

Aug 12, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC PMC

Compact Versal Adaptive SoC for the Software Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

3 days

Oct 28, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC PMC

Compact Versal Adaptive SoC for the Hardware Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Munich

3 days

Jul 10, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC

Compact Versal Adaptive SoC for the Hardware Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Stuttgart

3 days

Oct 16, 2024

Info

Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC

Compact Embedded Linux

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Munich

3 days

Jun 17, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Yocto tool flow Zynq SoC

Compact Embedded Linux

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Stuttgart

3 days

Sep 02, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Yocto tool flow Zynq SoC

Compact Embedded Linux

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

3 days

Nov 05, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Yocto tool flow Zynq SoC

Advanced Zynq UltraScale+ MPSoC for the Hardware Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

3 days

Jun 12, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE

Advanced Zynq UltraScale+ MPSoC for the Hardware Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

3 days

Sep 25, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE

Advanced Zynq UltraScale+ MPSoC for the Hardware Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Stuttgart

3 days

Dec 16, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE

Advanced Versal Adaptive SoC AI Engine

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

3 days

Sep 09, 2024

Info

Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP Acceleration & AI

Advanced Versal Adaptive SoC AI Engine

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Munich

3 days

Dec 04, 2024

Info

Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP Acceleration & AI

UVM Testbench Made Easy

WO (Workshop)

Programming Languages

Berlin

2 days

Jul 25, 2024

Info

FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions

UVM Testbench Made Easy

WO (Workshop)

Programming Languages

Freiburg

2 days

Oct 24, 2024

Info

FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions

SystemVerilog Advanced Verification for FPGA Design

WO (Workshop)

Programming Languages

Berlin

3 days

Jul 22, 2024

Info

FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis

SystemVerilog Advanced Verification for FPGA Design

WO (Workshop)

Programming Languages

Freiburg

3 days

Oct 21, 2024

Info

FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis

Compact VHDL for Synthesis

WO (Workshop)

Programming Languages

Stuttgart

3 days

Sep 02, 2024

Info

FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado

Compact VHDL for Synthesis

WO (Workshop)

Programming Languages

Munich

3 days

Nov 04, 2024

Info

FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado

Compact VHDL for Simulation

WO (Workshop)

Programming Languages

Stuttgart

2 days

Sep 05, 2024

Info

FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation

Compact VHDL for Simulation

WO (Workshop)

Programming Languages

Munich

2 days

Nov 07, 2024

Info

FPGA HDL VHDL Vivado Language Verification Hardware FPGA Programmable Logic Simulation

Compact Python for Embedded

WO (Workshop)

Programming Languages

Freiburg

3 days

Jun 24, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Compact Python for Embedded

WO (Workshop)

Programming Languages

Frankfurt / Main

3 days

Sep 23, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Compact Python for Embedded

WO (Workshop)

Programming Languages

Berlin

3 days

Nov 25, 2024

Info

FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library

Designing with Ethernet MAC Controllers

WO (Workshop)

Connectivity

Berlin

2 days

Sep 11, 2024

Info

Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP

Designing with Ethernet MAC Controllers

WO (Workshop)

Connectivity

Freiburg

2 days

Nov 21, 2024

Info

Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP

Compact Zynq UltraScale+ RFSoC

WO (Workshop)

Connectivity

Frankfurt / Main

3 days

Sep 16, 2024

Info

RFSoC ADC DAC RF UltraScale+ Data Converter

Compact Zynq UltraScale+ RFSoC

WO (Workshop)

Connectivity

Munich

3 days

Dec 09, 2024

Info

RFSoC ADC DAC RF UltraScale+ Data Converter

Compact Versal Adaptive SoC: Power and Board Design

WO (Workshop)

Connectivity

3 days

all year on request

Info

Embedded ACAP board design integrity power Versal Cortex-A72 Cortex-R5 NoC DDR4 AXI XPE power design Power Supply PDM Signal Integrity Reflection Crosstalk IBIS

Compact Versal Adaptive SoC: Connectivity

WO (Workshop)

Connectivity

Stuttgart

3 days

Aug 12, 2024

Info

Versal High-Speed Interfaces ACAP 10GE 100GE 400GE MAC PCS FEC transceiver PLL hard IP Aurora DDR4 memory interface VCK190 Gigabit Ethernet

Compact Versal Adaptive SoC: Connectivity

WO (Workshop)

Connectivity

Frankfurt / Main

3 days

Nov 04, 2024

Info

Versal High-Speed Interfaces ACAP 10GE 100GE 400GE MAC PCS FEC transceiver PLL hard IP Aurora DDR4 memory interface VCK190 Gigabit Ethernet

Compact UltraScale: Serial Transceivers

WO (Workshop)

Connectivity

Frankfurt / Main

3 days

Sep 23, 2024

Info

UltraScale Serial Transceiver GTX GTH GTY 8B/10B 64B/66B 64B/67B UltraScale+ gearbox PLL KCU105

Compact UltraScale: High-Speed Memory Interfacing

WO (Workshop)

Connectivity

3 days

all year on request

Info

7Series DDR3 memory Memory Controller PCB Design PCB Design Rules Debugging DDR3 UltraScale UltraScale+ DDR4 memory

Compact UltraScale: Board Design and Signal Integrity

WO (Workshop)

Connectivity

3 days

all year on request

Info

UltraScale Power Supply board design power integrity Signal Integrity Reflection Crosstalk HyperLynx IBIS AMI Models PCB Simulation High-Speed Interfaces Transceiver PCI Express DDR4 PCB Design UltraScale+ board design power design Power Supply XPE Signal Integrity Reflection Crosstalk IBIS

AXI Interface Technology

WO (Workshop)

Connectivity

Frankfurt / Main

2 days

Jun 26, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

WO (Workshop)

Connectivity

Berlin

2 days

Sep 09, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

WO (Workshop)

Connectivity

Munich

2 days

Nov 28, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

Compact UltraScale: Integrated PCI Express Systems

WO (Workshop)

Connectivity

Munich

3 days

Sep 02, 2024

Info

UltraScale PCI Express Integrated Block for PCI Express Gen3 PL PCIe UltraScale+ PCIe endpoint root port DMA KCU105

Compact UltraScale: Integrated PCI Express Systems

WO (Workshop)

Connectivity

Berlin

3 days

Dec 02, 2024

Info

UltraScale PCI Express Integrated Block for PCI Express Gen3 PL PCIe UltraScale+ PCIe endpoint root port DMA KCU105

Compact Vivado Design Suite Tool Flow

WO (Workshop)

Development
Tools & Methodology

Stuttgart

2 days

Sep 16, 2024

Info

Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode

Compact Vivado Design Suite Tool Flow

WO (Workshop)

Development
Tools & Methodology

Munich

2 days

Nov 04, 2024

Info

Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode

Compact Timing Constraints and Analysis

WO (Workshop)

Development
Tools & Methodology

Stuttgart

3 days

Sep 18, 2024

Info

Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction

Compact Timing Constraints and Analysis

WO (Workshop)

Development
Tools & Methodology

Munich

3 days

Nov 06, 2024

Info

Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction

Git for EDA Tool Flows

WO (Workshop)

Development
Tools & Methodology

Berlin

3 days

Jun 10, 2024

Info

Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging

Git for EDA Tool Flows

WO (Workshop)

Development
Tools & Methodology

Munich

3 days

Sep 09, 2024

Info

Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging

Git for EDA Tool Flows

WO (Workshop)

Development
Tools & Methodology

Freiburg

3 days

Dec 16, 2024

Info

Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging

FPGA Power Optimization

WO (Workshop)

Development
Tools & Methodology

2 days

all year on request

Info

FPGA Power Vivado Kintex XCE clocking

Dynamic Function eXchange (DFX)

WO (Workshop)

Development
Tools & Methodology

Stuttgart

2 days

Jul 08, 2024

Info

FPGA DFX Vivado partial configuration functions Black Box Floorplaning

Dynamic Function eXchange (DFX)

WO (Workshop)

Development
Tools & Methodology

Freiburg

2 days

Oct 01, 2024

Info

FPGA DFX Vivado partial configuration functions Black Box Floorplaning

Designing with the Xilinx Analog Mixed Signal Solution

WO (Workshop)

Development
Tools & Methodology

2 days

all year on request

Info

FPGA AMS Vivado XADC DAC

Debugging Techniques Using the Vivado Logic Analyzer

WO (Workshop)

Development
Tools & Methodology

Freiburg

2 days

Jun 26, 2024

Info

Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation

Debugging Techniques Using the Vivado Logic Analyzer

WO (Workshop)

Development
Tools & Methodology

Stuttgart

2 days

Sep 12, 2024

Info

Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation

Debugging Techniques Using the Vivado Logic Analyzer

WO (Workshop)

Development
Tools & Methodology

Frankfurt / Main

2 days

Dec 02, 2024

Info

Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation

Compact Vitis for the Software Designer

WO (Workshop)

Development
Tools & Methodology

Berlin

3 days

Sep 17, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging

Compact Vitis for the Software Designer

WO (Workshop)

Development
Tools & Methodology

Munich

3 days

Dec 16, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging

Compact Vitis for Acceleration

WO (Workshop)

Development
Tools & Methodology

Freiburg

3 days

Aug 12, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging

Compact Vitis for Acceleration

WO (Workshop)

Development
Tools & Methodology

Frankfurt / Main

3 days

Nov 20, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging

Compact Vitis AI

WO (Workshop)

Development
Tools & Methodology

Freiburg

3 days

Jun 10, 2024

Info

Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software

Compact Vitis AI

WO (Workshop)

Development
Tools & Methodology

Stuttgart

3 days

Sep 23, 2024

Info

Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software

Compact Vitis AI

WO (Workshop)

Development
Tools & Methodology

Berlin

3 days

Nov 04, 2024

Info

Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software

Compact FPGA Circuit Design Technique

WO (Workshop)

Development
Tools & Methodology

Stuttgart

3 days

Aug 05, 2024

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+

Compact FPGA Circuit Design Technique

WO (Workshop)

Development
Tools & Methodology

Berlin

3 days

Oct 09, 2024

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+

Compact Vitis HLS

WO (Workshop)

DSP & Image Processing

Freiburg

3 days

Aug 27, 2024

Info

Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface

Compact Vitis HLS

WO (Workshop)

DSP & Image Processing

Stuttgart

3 days

Nov 27, 2024

Info

Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface

Compact DSP Design for Versal Using Vitis Model Composer

WO (Workshop)

DSP & Image Processing

3 days

all year on request

Info

DSP Mathworks Matlab Tool Flow FPGA

Compact DSP Design for FPGAs Using Vitis Model Composer

WO (Workshop)

DSP & Image Processing

Freiburg

3 days

Sep 02, 2024

Info

DSP Mathworks Matlab Tool Flow FPGA

Compact DSP Design for FPGAs Using Vitis Model Composer

WO (Workshop)

DSP & Image Processing

Berlin

3 days

Dec 16, 2024

Info

DSP Mathworks Matlab Tool Flow FPGA

Zynq 7000 SoC for the System Architect

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

2 days

all year on request

Info

Embedded Architecture Vivado Vitis Zynq SoC Peripherals Memory

Zynq UltraScale+ MPSoC for the System Architect

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Freiburg

2 days

Sep 12, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE

Zynq UltraScale+ MPSoC for the System Architect

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Munich

2 days

Dec 19, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE

Versal Adaptive SoC for the System Architect

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Stuttgart

2 days

Aug 01, 2024

Info

Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI

Versal Adaptive SoC for the System Architect

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Munich

2 days

Nov 18, 2024

Info

Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI

Essentials of Microprocessors

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

1 day

all year on request

Info

Embedded Microcontroller Processor Compiler Cache Linker Debugger Vitis

Compact UltraScale/UltraScale+

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Freiburg

2 days

Jun 24, 2024

Info

FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO

Compact UltraScale/UltraScale+

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Frankfurt / Main

2 days

Sep 26, 2024

Info

FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO

Compact UltraScale/UltraScale+

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Stuttgart

2 days

Nov 21, 2024

Info

FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO

Compact FPGA 7 Series

WO (Workshop)

AMD (Adaptive) SoC, MPSoC & FPGA Architecture

2 days

on request all year tbd

Info

FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP 7 series IO

showing: 1 to 2 (2)

How can we help?

Contact

FAQ

01. Can you help me with reserving the room?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

02. What times in the day do courses start and end?

Our face-to-face courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours. For online courses, the start is also at 9 a.m. (CET/CEST), but they end at 2:30 p.m.. The total course time per day is 4 and a half hours plus breaks.

03. Are course materials provided?

All participants of paid courses will receive English training materials in electronic or paper form.

04. Will I receive a course certificate?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

05. Can I pay with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

06. What are the options for payment?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

07. What is the deadline for payment?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

08. What are the options for cancelling?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

09. When will I receive a firm commitment as to whether the course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

10. How many participants are required for a course to be given/what is the minimum number of participants?

We generally offer courses for 5 or more people. That means that if you would like to book a course at your premises, you need 5 people to register or need to pay the amount for 5 participants, even if fewer people attend.

11. Can I book a course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

12. What language is the course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.