Menu

Zynq UltraScale+ MPSoC for the System Architect

Workshop


Online Live

This course provides system architects with an overview of the capabilities and support for the Zynq™ UltraScale+™ MPSoC family.

The emphasis is on leveraging the Arm® Cortex®-APU, RPU, and Platform Management Unit (PMU) capabilities. A separation of protected software tasks is needed when several OS are running in a system securely and safely.
A power-management concept in hard- and software will be demonstrated for getting higher reliability and optimized power consumption.

Due to accompanying exercises, the course offers in-depth and practice-oriented training. Attendees of the online live course will do the practical exercises in the afternoon on their own.

Course language: German (English possible on request)

Portrait von Michael Schwarz

Contact

Michael Schwarz

+49 7664 91313-15

michael.schwarz@plc2.de

Details

Applicable technologies

AMD Zynq™ UltraScale+™ MPSoC and RFSoC,
Kria™ SoMs

Requirements

Conceptual understanding of embedded processing systems.
C or C++ programming experience, including general debugging techniques

Duration

2 days

Fee (net per person)

€ 1,700

Inclusive

Training material
Plus beverages during breaks
Lunch

Agenda

01

Zynq™ UltraScale+™ MPSoC architecture overview

02

Hardware-software virtualization

03

QEMU for application development and debugging

04

Isolation for security and safety demands

05

Power management and platform mangement using the PMU

06

Caching and system coherency

07

DDR memory management and QoS

08

Booting concepts

09

Boot loading and boot images

10

Zynq™ UltraScale+™ MPSoC ecosystem support

Dates

Zynq UltraScale+ MPSoC for the System Architect

WO

Frankfurt / Main

Jun 03, 2024

Book now

Zynq UltraScale+ MPSoC for the System Architect

WO

Freiburg

Sep 12, 2024

Book now

Zynq UltraScale+ MPSoC for the System Architect

WO

Munich

Dec 19, 2024

Book now

Booking

DE EN

Company

Contact Person

Request / Offer

Billing Address

Billing Person

Participant(s)

Fee

Participant

 

€ 1,700

Course

Zynq UltraScale+ MPSoC for the System Architect_WO

Total fee

€ 1,700

*Required field

Unternehmen

Ansprechpartner:in

Anfrage / Angebot

Rechnungsanschrift

Ansprechpartner:in

Teilnehmer:innnen

Kosten

Teilnehmer:in

 

€ 1,700

Kurs

Zynq UltraScale+ MPSoC for the System Architect_WO

Gesamtbetrag

€ 1,700

*Pflichtfeld

This might also interest you...

Course Format Category Location Duration Date

Professional Zynq UltraScale+ MPSoC

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

5 days

Dec 02, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Professional Zynq UltraScale+ MPSoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

5 days

Jun 03, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Professional Zynq UltraScale+ MPSoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

5 days

Sep 16, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Professional Zynq UltraScale+ MPSoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

5 days

Dec 02, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Compact Embedded Linux

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

3 days

Nov 05, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Yocto tool flow Zynq SoC

Compact Embedded Linux

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Munich

3 days

Jun 17, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Yocto tool flow Zynq SoC

Compact Embedded Linux

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Stuttgart

3 days

Sep 02, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Yocto tool flow Zynq SoC

Compact Embedded Linux

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

3 days

Nov 05, 2024

Info

Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Yocto tool flow Zynq SoC

Professional FPGA Circuit Design Technique

OL (Online Live)

Development
Tools & Methodology

Online

5 days

Nov 04, 2024

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+

Professional FPGA Circuit Design Technique

PW (Power Workshop)

Development
Tools & Methodology

Freiburg

5 days

Jul 15, 2024

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+

Professional FPGA Circuit Design Technique

PW (Power Workshop)

Development
Tools & Methodology

Freiburg

5 days

Nov 04, 2024

Info

FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+

Debugging Techniques Using the Vivado Logic Analyzer

OL (Online Live)

Development
Tools & Methodology

Online

2 days

Jun 26, 2024

Info

Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation

Debugging Techniques Using the Vivado Logic Analyzer

OL (Online Live)

Development
Tools & Methodology

Online

2 days

Dec 02, 2024

Info

Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation

Debugging Techniques Using the Vivado Logic Analyzer

WO (Workshop)

Development
Tools & Methodology

Freiburg

2 days

Jun 26, 2024

Info

Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation

Debugging Techniques Using the Vivado Logic Analyzer

WO (Workshop)

Development
Tools & Methodology

Stuttgart

2 days

Sep 12, 2024

Info

Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation

Debugging Techniques Using the Vivado Logic Analyzer

WO (Workshop)

Development
Tools & Methodology

Frankfurt / Main

2 days

Dec 02, 2024

Info

Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation

AXI Interface Technology

OL (Online Live)

Connectivity

Online

2 days

Aug 01, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

OL (Online Live)

Connectivity

Online

2 days

Dec 09, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

WO (Workshop)

Connectivity

Frankfurt / Main

2 days

Jun 26, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

WO (Workshop)

Connectivity

Berlin

2 days

Sep 09, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

WO (Workshop)

Connectivity

Munich

2 days

Nov 28, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

showing: 1 to 2 (2)

How can we help?

Contact

FAQ

01. Can you help me with reserving the room?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

02. What times in the day do courses start and end?

Our face-to-face courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours. For online courses, the start is also at 9 a.m. (CET/CEST), but they end at 2:30 p.m.. The total course time per day is 4 and a half hours plus breaks.

03. Are course materials provided?

All participants of paid courses will receive English training materials in electronic or paper form.

04. Will I receive a course certificate?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

05. Can I pay with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

06. What are the options for payment?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

07. What is the deadline for payment?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

08. What are the options for cancelling?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

09. When will I receive a firm commitment as to whether the course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

10. How many participants are required for a course to be given/what is the minimum number of participants?

We generally offer courses for 5 or more people. That means that if you would like to book a course at your premises, you need 5 people to register or need to pay the amount for 5 participants, even if fewer people attend.

11. Can I book a course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

12. What language is the course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.