PLC2 Training Format

Online Live Training
around FPGAs and MPSoCs

Our PLC2 online training courses offer you the opportunity to acquire technical expertise in the desired and required depth - from your home or your office.
Thanks to an advanced technical setup, you can complete the exercises - software and hardware - in real-time from any location of your choice. This interactive and engaging format not only enhances your learning experience but also ensures that you can address any questions or challenges on the spot, making the learning process more efficient and effective.

Online Live in a Nutshell

Online event

Learn and get trained from behind your desk. Ask questions directly. No need to travel and lose valuable time.

Self-learning experience

Develop your knowledge by attending targeted classes. Complete the exercises in real-time with remote access.

Format-independant expert learning

Nearly all courses are available as Online Live trainings, giving you the flexibility to join from anywhere. In compact two- to five-day workshops, you can build up deep technical expertise in your chosen topic.

Save costs and time

With the Online Live format, you join interactive courses directly from your desk at home or workplace, combining efficiency with hands-on learning.

Upcoming Online Lives

Course	Format	Category	Location	Duration	Date
NEW \| AMD Ross™ Agentic AI Assistant From Ground Up	OL (Online Live)	Development Tools & Methodology	Online	1 day	Oct 27, 2026	Info AI embedded development agentic ai
NEW \| Edge AI Inference Deployment with AMD Vitis AI	OL (Online Live)	Development Tools & Methodology	Online	1 day	Nov 17, 2026	Info AI vitis deep learning versal gen 2 neural networks
Compact Timing Constraints and Analysis \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 18, 2026	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Feb 17, 2027	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Jun 23, 2027	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 08, 2027	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 24, 2027	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Professional FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Nov 02, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+ timing constraints
Professional FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Feb 22, 2027	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+ timing constraints
Professional FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Apr 12, 2027	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+ timing constraints
Professional FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Jul 05, 2027	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+ timing constraints
Professional FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Nov 15, 2027	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+ timing constraints
Compact Spartan UltraScale+ \| Online	OL (Online Live)	AMD Architecture	Online	3 days	Nov 11, 2026	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact Spartan UltraScale+ \| Online	OL (Online Live)	AMD Architecture	Online	3 days	Mar 22, 2027	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact Spartan UltraScale+ \| Online	OL (Online Live)	AMD Architecture	Online	3 days	Jul 21, 2027	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact Spartan UltraScale+ \| Online	OL (Online Live)	AMD Architecture	Online	3 days	Nov 03, 2027	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Scripting the AMD Hardware Design Flow Using Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 23, 2026	Info Vivado TCL Script scripting xdc tcl-script non-project mode batch
Scripting the AMD Hardware Design Flow Using Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Mar 08, 2027	Info Vivado TCL Script scripting xdc tcl-script non-project mode batch
Scripting the AMD Hardware Design Flow Using Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Jun 09, 2027	Info Vivado TCL Script scripting xdc tcl-script non-project mode batch
Scripting the AMD Hardware Design Flow Using Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 20, 2027	Info Vivado TCL Script scripting xdc tcl-script non-project mode batch
Scripting the AMD Hardware Design Flow Using Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 15, 2027	Info Vivado TCL Script scripting xdc tcl-script non-project mode batch
Compact SystemVerilog for Synthesis \| Online	OL (Online Live)	Programming Languages	Online	3 days	Oct 26, 2026	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact SystemVerilog for Synthesis \| Online	OL (Online Live)	Programming Languages	Online	3 days	Feb 09, 2027	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact SystemVerilog for Synthesis \| Online	OL (Online Live)	Programming Languages	Online	3 days	Apr 05, 2027	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact SystemVerilog for Synthesis \| Online	OL (Online Live)	Programming Languages	Online	3 days	Jul 12, 2027	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Compact SystemVerilog for Synthesis \| Online	OL (Online Live)	Programming Languages	Online	3 days	Oct 20, 2027	Info FPGA HDL Verilog SystemVerilog Language Description Hardware FPGA Programmable Logic Synthese Simulation Implementierung bit Bitstream Design Verification Synthesis
Advanced VHDL \| Online	OL (Online Live)	Programming Languages	Online	3 days	Oct 19, 2026	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL \| Online	OL (Online Live)	Programming Languages	Online	3 days	Dec 14, 2026	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL \| Online	OL (Online Live)	Programming Languages	Online	3 days	Mar 22, 2027	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL \| Online	OL (Online Live)	Programming Languages	Online	3 days	Jul 05, 2027	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL \| Online	OL (Online Live)	Programming Languages	Online	3 days	Oct 04, 2027	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Advanced VHDL \| Online	OL (Online Live)	Programming Languages	Online	3 days	Dec 13, 2027	Info Advanced VHDL OSVVM sytnhesis simulation UVVM VUnit VHDL-2019 EDA tool
Compact MicroBlaze V System Design \| Online	OL (Online Live)	Embedded Development	Online	3 days	all year on request	Info Embedded MicroBlaze System Design Systems FPGA hardware software AMD tool tools custom peripheral application debugging integration microprocessor microprocessors Vivado Vitis
Compact VHDL Testbenches and Verification with OSVVM \| Online	OL (Online Live)	Programming Languages	Online	3 days	Mar 10, 2027	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Compact VHDL Testbenches and Verification with OSVVM \| Online	OL (Online Live)	Programming Languages	Online	3 days	May 19, 2027	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Compact VHDL Testbenches and Verification with OSVVM \| Online	OL (Online Live)	Programming Languages	Online	3 days	Aug 03, 2027	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Compact VHDL Testbenches and Verification with OSVVM \| Online	OL (Online Live)	Programming Languages	Online	3 days	Oct 18, 2027	Info FPGA HDL VHDL HDL Language Verification Hardware FPGA Programmable Logic Simulation Open-Source Open Source Method AXI VIP IP Simulator
Advanced Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Oct 14, 2026	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Jan 25, 2027	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Apr 19, 2027	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Jul 14, 2027	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Oct 13, 2027	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Professional Versal Adaptive SoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	Nov 02, 2026	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI
Professional Versal Adaptive SoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	Mar 01, 2027	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI
Professional Versal Adaptive SoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	Jun 21, 2027	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI
Professional Versal Adaptive SoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	Sep 06, 2027	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI
Professional Versal Adaptive SoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	Nov 08, 2027	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC Acceleration & AI
Compact Zynq 7000 SoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	all year on request	Info Embedded Architecture Vivado Vitis SoC Cortex-A9 Processor Cache PetaLinux Linux PS AXI Processing System
Professional Zynq 7000 SoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	all year on request	Info Embedded Architecture Vivado Vitis Zynq SoC Boot Software C C++ AXI Configuration System Integration Debugging AXI PS Processing System
Professional Zynq UltraScale+ MPSoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	Dec 07, 2026	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Professional Zynq UltraScale+ MPSoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	Mar 01, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Professional Zynq UltraScale+ MPSoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	Jun 21, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Professional Zynq UltraScale+ MPSoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	Sep 06, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Professional Zynq UltraScale+ MPSoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	Dec 06, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Expert Zynq 7000 SoC \| Online	OL (Online Live)	Embedded Development	Online	5 days	all year on request	Info Embedded Architecture Vivado Vitis SoC Cortex-A9 Processor Cache PetaLinux IP-Integrator Linux PS AXI PS Processing System
Expert Versal Adaptive SoC AI Engine \| Online	OL (Online Live)	Embedded Development	Online	5 days	Oct 19, 2026	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP , Acceleration & AI Artifical Intelligence AI KI
Expert Versal Adaptive SoC AI Engine \| Online	OL (Online Live)	Embedded Development	Online	5 days	Jan 25, 2027	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP , Acceleration & AI Artifical Intelligence AI KI
Expert Versal Adaptive SoC AI Engine \| Online	OL (Online Live)	Embedded Development	Online	5 days	Apr 19, 2027	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP , Acceleration & AI Artifical Intelligence AI KI
Expert Versal Adaptive SoC AI Engine \| Online	OL (Online Live)	Embedded Development	Online	5 days	Jul 19, 2027	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP , Acceleration & AI Artifical Intelligence AI KI
Expert Versal Adaptive SoC AI Engine \| Online	OL (Online Live)	Embedded Development	Online	5 days	Oct 18, 2027	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP , Acceleration & AI Artifical Intelligence AI KI
Embedded Linux Driver Development \| Online	OL (Online Live)	Embedded Development	Online	3 days	all year on request	Info Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Driver Character Yocto tool flow Zynq
Embedded Design with PetaLinux Tools \| Online	OL (Online Live)	Embedded Development	Online	2 days	all year on request	Info Embedded Linux PetaLinux build rootfs kernel driver layer DeviceTree Device-Tree Boot
Developing Multimedia Solutions with the VCU and GStreamer \| Online	OL (Online Live)	Embedded Development	Online	2 days	Oct 20, 2026	Info SoM Vision Video streaming data application codec Kria Embedded Multimedia Gstreamer VCU Camera PetaLinux Linux Kernel
Developing Multimedia Solutions with the VCU and GStreamer \| Online	OL (Online Live)	Embedded Development	Online	2 days	Feb 22, 2027	Info SoM Vision Video streaming data application codec Kria Embedded Multimedia Gstreamer VCU Camera PetaLinux Linux Kernel
Developing Multimedia Solutions with the VCU and GStreamer \| Online	OL (Online Live)	Embedded Development	Online	2 days	May 24, 2027	Info SoM Vision Video streaming data application codec Kria Embedded Multimedia Gstreamer VCU Camera PetaLinux Linux Kernel
Developing Multimedia Solutions with the VCU and GStreamer \| Online	OL (Online Live)	Embedded Development	Online	2 days	Jul 19, 2027	Info SoM Vision Video streaming data application codec Kria Embedded Multimedia Gstreamer VCU Camera PetaLinux Linux Kernel
Developing Multimedia Solutions with the VCU and GStreamer \| Online	OL (Online Live)	Embedded Development	Online	2 days	Oct 05, 2027	Info SoM Vision Video streaming data application codec Kria Embedded Multimedia Gstreamer VCU Camera PetaLinux Linux Kernel
Compact Zynq 7000 SoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	all year on request	Info Embedded Architecture Vivado Vitis Zynq SoC Platform Hardware C AXI PS Processing System
Advanced Zynq UltraScale+ MPSoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Dec 01, 2026	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Advanced Zynq UltraScale+ MPSoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Mar 22, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Advanced Zynq UltraScale+ MPSoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Jun 09, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Advanced Zynq UltraScale+ MPSoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Sep 27, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Advanced Zynq UltraScale+ MPSoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Dec 01, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis
Compact Zynq UltraScale+ MPSoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Nov 11, 2026	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis A53 R5
Compact Zynq UltraScale+ MPSoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Feb 09, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis A53 R5
Compact Zynq UltraScale+ MPSoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	May 24, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis A53 R5
Compact Zynq UltraScale+ MPSoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Aug 10, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis A53 R5
Compact Zynq UltraScale+ MPSoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Nov 08, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis A53 R5
Compact Zynq UltraScale+ MPSoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Nov 02, 2026	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE
Compact Zynq UltraScale+ MPSoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Feb 10, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE
Compact Zynq UltraScale+ MPSoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	May 03, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE
Compact Zynq UltraScale+ MPSoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Aug 17, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE
Compact Zynq UltraScale+ MPSoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Nov 02, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE
Compact Versal Adaptive SoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Feb 22, 2027	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC PMC
Compact Versal Adaptive SoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	May 24, 2027	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC PMC
Compact Versal Adaptive SoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Aug 23, 2027	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC PMC
Compact Versal Adaptive SoC for the Software Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Oct 26, 2027	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC PMC
Compact Versal Adaptive SoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Jan 20, 2027	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC
Compact Versal Adaptive SoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Apr 14, 2027	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC
Compact Versal Adaptive SoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Jul 05, 2027	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC
Compact Versal Adaptive SoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	Oct 11, 2027	Info Embedded ACAP Vitis tool flow Vivado Versal Cortex-A72 Cortex-R5 NoC CIPS AXI PMC
Compact Embedded Linux \| Online	OL (Online Live)	Embedded Development	Online	3 days	all year on request	Info Embedded PetaLinux Vitis Linux OS Operating System Open Source OSS Driver Application Library Software Kernel Debugging Performance Boot Bootflow elf c c++ c/c++ Device Tree Devicetree Device-Tree Yocto tool flow Zynq SoC
Advanced Zynq UltraScale+ MPSoC for the Hardware Designer \| Online	OL (Online Live)	Embedded Development	Online	3 days	all year on request	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Peripheral PS PMU AXI Power IP-Integrator ACE
Advanced Versal Adaptive SoC AI Engine \| Online	OL (Online Live)	Embedded Development	Online	3 days	Dec 09, 2026	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP Acceleration & AI Artifical Intelligence AI KI
Advanced Versal Adaptive SoC AI Engine \| Online	OL (Online Live)	Embedded Development	Online	3 days	Mar 10, 2027	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP Acceleration & AI Artifical Intelligence AI KI
Advanced Versal Adaptive SoC AI Engine \| Online	OL (Online Live)	Embedded Development	Online	3 days	Jun 28, 2027	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP Acceleration & AI Artifical Intelligence AI KI
Advanced Versal Adaptive SoC AI Engine \| Online	OL (Online Live)	Embedded Development	Online	3 days	Sep 28, 2027	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP Acceleration & AI Artifical Intelligence AI KI
Advanced Versal Adaptive SoC AI Engine \| Online	OL (Online Live)	Embedded Development	Online	3 days	Dec 01, 2027	Info Embedded ACAP CNN neuronal network ML KI Vitis AI Versal AI Engine Vector Processing DSP AI ML Acceleration DSP Acceleration & AI Artifical Intelligence AI KI
UVM Testbench Made Easy \| Online	OL (Online Live)	Programming Languages	Online	2 days	all year on request	Info FPGA HDL Verilog SystemVerilog Language Verification Hardware FPGA Programmable Logic Simulation UVM Universal Verification Methodology UVM Framework Transactions
SystemVerilog Advanced Verification for FPGA Design \| Online	OL (Online Live)	Programming Languages	Online	3 days	all year on request	Info FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis
Professional VHDL \| Online	OL (Online Live)	Programming Languages	Online	5 days	Dec 07, 2026	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL \| Online	OL (Online Live)	Programming Languages	Online	5 days	Feb 01, 2027	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL \| Online	OL (Online Live)	Programming Languages	Online	5 days	May 10, 2027	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL \| Online	OL (Online Live)	Programming Languages	Online	5 days	Jul 26, 2027	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL \| Online	OL (Online Live)	Programming Languages	Online	5 days	Oct 18, 2027	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL \| Online	OL (Online Live)	Programming Languages	Online	5 days	Dec 06, 2027	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL Testbenches and Verification with OSVVM \| Online	OL (Online Live)	Programming Languages	Online	5 days	Nov 09, 2026	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional VHDL Testbenches and Verification with OSVVM \| Online	OL (Online Live)	Programming Languages	Online	5 days	Feb 15, 2027	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional VHDL Testbenches and Verification with OSVVM \| Online	OL (Online Live)	Programming Languages	Online	5 days	Jun 07, 2027	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional VHDL Testbenches and Verification with OSVVM \| Online	OL (Online Live)	Programming Languages	Online	5 days	Sep 06, 2027	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional VHDL Testbenches and Verification with OSVVM \| Online	OL (Online Live)	Programming Languages	Online	5 days	Nov 15, 2027	Info FPGA HDL VHDL OSVVM Language Verification Hardware FPGA Programmable Logic Simulation Self-Checking Randomization Verification Component Verification Model Transaction Based Modus Bus Functional Model BFM AXI
Professional Python for Embedded \| Online	OL (Online Live)	Programming Languages	Online	5 days	Nov 23, 2026	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
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Compact VHDL for Synthesis \| Online	OL (Online Live)	Programming Languages	Online	3 days	Nov 23, 2026	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
Compact VHDL for Synthesis \| Online	OL (Online Live)	Programming Languages	Online	3 days	Mar 01, 2027	Info FPGA HDL VHDL Synthesis Language Description Hardware FPGA Programmable Logic Synthese Implementierung bit Bitstream Introduction Vivado
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Compact Python for Embedded \| Online	OL (Online Live)	Programming Languages	Online	3 days	Nov 23, 2026	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact Python for Embedded \| Online	OL (Online Live)	Programming Languages	Online	3 days	Mar 15, 2027	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact Python for Embedded \| Online	OL (Online Live)	Programming Languages	Online	3 days	Jun 07, 2027	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
Compact Python for Embedded \| Online	OL (Online Live)	Programming Languages	Online	3 days	Sep 20, 2027	Info FPGA SoC MPSoC Script Scripting Automation Tool CI Continuous Integration Build System Embedded open-source open source interpreter object oriented library
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Compact Versal Adaptive SoC: Power and Board Design \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	3 days	all year on request	Info Embedded ACAP board design integrity power Versal Cortex-A72 Cortex-R5 NoC DDR4 AXI XPE power design Power Supply PDM Signal Integrity Reflection Crosstalk IBIS
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AXI Interface Technology \| Online	OL (Online Live)	FPGA Connectivity & Protocols	Online	2 days	Nov 02, 2026	Info FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance
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Compact Vivado Design Suite Tool Flow \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Nov 16, 2026	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
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Professional Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Dec 14, 2026	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
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FPGA Power Optimization \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	all year on request	Info FPGA Power Vivado Kintex XCE clocking
Easy Start FPGA Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Nov 23, 2026	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
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Dynamic Function eXchange (DFX) \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Jan 28, 2027	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Dynamic Function eXchange (DFX) \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Apr 12, 2027	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Dynamic Function eXchange (DFX) \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Jul 12, 2027	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Dynamic Function eXchange (DFX) \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Oct 11, 2027	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Debugging Techniques Using the Vivado Logic Analyzer \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Dec 01, 2026	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
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Continuous Integration for EDA Tools \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Feb 22, 2027	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
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Compact Vitis for the Software Designer \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Dec 16, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
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Compact Edge IoT \| Online	OL (Online Live)	Embedded Development	Online	3 days	Dec 01, 2026	Info Edge AI Design Flow Vitis Vivado Phyton AMD Adaptive Socs Alveo Cards deep neural Networks Zynq UltraScale+ MPSoC
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Compact FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Oct 21, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
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Compact Vitis HLS \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	Nov 18, 2026	Info Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface
Compact Vitis HLS \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	Feb 03, 2027	Info Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface
Compact Vitis HLS \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	May 10, 2027	Info Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface
Compact Vitis HLS \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	Aug 18, 2027	Info Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface
Compact Vitis HLS \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	Nov 15, 2027	Info Design Entry Vitis HLS Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library High Level Synthesis c/c++ Co-Simulation IP AXI interface
Professional DSP Design Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	5 days	Dec 14, 2026	Info DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox
Professional DSP Design Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	5 days	Feb 22, 2027	Info DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox
Professional DSP Design Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	5 days	Jun 21, 2027	Info DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox
Professional DSP Design Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	5 days	Sep 13, 2027	Info DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox
Professional DSP Design Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	5 days	Dec 06, 2027	Info DSP Mathworks Matlab Tool Flow Simulink Filter FPGA Sampling Streaming System Generator Toolbox
Compact DSP Design for Versal Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	all year on request	Info DSP Mathworks Matlab Tool Flow FPGA
Compact DSP Design for FPGAs Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	Dec 14, 2026	Info DSP Mathworks Matlab Tool Flow FPGA
Compact DSP Design for FPGAs Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	Feb 22, 2027	Info DSP Mathworks Matlab Tool Flow FPGA
Compact DSP Design for FPGAs Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	Jun 21, 2027	Info DSP Mathworks Matlab Tool Flow FPGA
Compact DSP Design for FPGAs Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	Sep 13, 2027	Info DSP Mathworks Matlab Tool Flow FPGA
Compact DSP Design for FPGAs Using Vitis Model Composer \| Online	OL (Online Live)	DSP & Image Processing	Online	3 days	Dec 06, 2027	Info DSP Mathworks Matlab Tool Flow FPGA
Zynq 7000 SoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	all year on request	Info Embedded Architecture Vivado Vitis Zynq SoC Peripherals Memory
Zynq UltraScale+ MPSoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Dec 14, 2026	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE
Zynq UltraScale+ MPSoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Mar 08, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE
Zynq UltraScale+ MPSoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Jun 07, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE
Zynq UltraScale+ MPSoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Sep 27, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE
Zynq UltraScale+ MPSoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Dec 13, 2027	Info Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor Protection PCIe PS PMU Power IP-Integrator AXI ACE
Versal Adaptive SoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Nov 16, 2026	Info Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI
Versal Adaptive SoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Jan 18, 2027	Info Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI
Versal Adaptive SoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Apr 12, 2027	Info Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI
Versal Adaptive SoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Aug 16, 2027	Info Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI
Versal Adaptive SoC for the System Architect \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Nov 10, 2027	Info Embedded ACAP Architecture Vivado Vitis Versal System Integration Cortex-A72 Cortex-R5 NoC DDR4 AXI Heterogenous Compute Acceleration & AI
Professional FPGA \| Online	OL (Online Live)	AMD Architecture	Online	5 days	Oct 26, 2026	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA \| Online	OL (Online Live)	AMD Architecture	Online	5 days	Feb 15, 2027	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA \| Online	OL (Online Live)	AMD Architecture	Online	5 days	May 10, 2027	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA \| Online	OL (Online Live)	AMD Architecture	Online	5 days	Jul 05, 2027	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA \| Online	OL (Online Live)	AMD Architecture	Online	5 days	Oct 25, 2027	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Essentials of Microprocessors \| Online	OL (Online Live)	AMD Architecture	Online	1 day	all year on request	Info Embedded Microcontroller Processor Compiler Cache Linker Debugger Vitis
Compact UltraScale/UltraScale+ \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Nov 11, 2026	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+ \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Mar 17, 2027	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+ \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Jun 07, 2027	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+ \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Sep 20, 2027	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+ \| Online	OL (Online Live)	AMD Architecture	Online	2 days	Nov 11, 2027	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact FPGA 7 Series \| Online	OL (Online Live)	AMD Architecture	Online	2 days	all year on request	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP 7 series IO
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Other Formats

In-House

Individual and modular course content
Exclusive format focused on team-specific challenges
Length and pace adapted to your schedule
On-site training at the location of your choice

EXPLORE

Webinar

Good overview of a topic
Technical focus
Online

EXPLORE

Seminar

1-day technical deep dive
Free of charge
For developers, department heads, and managers

EXPLORE

Easy Start

Perfect for beginners and project managers
With a focus on practical exercises

EXPLORE

Workshop

Compact 1- to 3-day workshop
Ideal for developers
Theory and practice

EXPLORE

Power Workshop

5-day workshop
Very extensive further training
Practice-oriented on PC and evaluation board
Detailed treatment of technical topics

EXPLORE

Long Term Education

3 months training
For engineers and technicians
Including comprehensive training material

EXPLORE

How can we help?

Contact

Call PLC2

+49 7664 91313-15

Send an e-mail

michael.schwarz@plc2.de

FAQ

01. Is the content of the PLC2 Online Live training sessions the same as the PLC2 Workshops or Power Workshops?

Yes, the content is the same. Only the hands-on exercises may be scaled down depending on the participants’ technical abilities.

02. What technical requirements must I meet in order to participate in a PLC2 Online Live training session?

You need a stable internet connection (min. ~1 Mbps), a computer or laptop, and access to a modern web browser or the GoTo Training app. Audio output is required, and a microphone is recommended for interaction.

03. Does PLC2 offer hybrid training sessions?

Depending on the required training course, we can try to accommodate your requests as best as possible.

04. In which countries is PLC2 an Authorized Training Provider (ATP) of AMD?

PLC2 is an ATP in Cyprus, Czech Republic, Germany, Greece, Hungary, Poland, Slovakia, Slovenia, Switzerland, and Turkey.

05. What does AMD ATP stand for?

AMD Authorized Training Providers (ATPs) are expert instructors specializing in all aspects of FPGA and embedded design from software to systems and beyond. Courses offered leverage training materials specifically developed by AMD engineers and enhanced further via the specialized knowledge and expertise of AMD ATP instructors.

06. Can the training content be customized to specific FPGA and embedded design project requirements?

Yes. On request, we create customized training courses that are precisely tailored to your company’s tools, processes, and methods. See also our In-House training format.

07. Are there hands-on exercises in PLC2 training courses?

Depending on the course format, hands-on exercises are included in most of the training sessions, especially in workshops, power workshops, and online live courses.

08. How can I register for a PLC2 training course?

Go to the page of your desired training course and click the button »Book workshop«. You will jump directly to the booking form. Fill out the form and click submit. You will receive a confirmation e-mail immediately.

09. Can you help me with booking a room for the duration of my PLC2 training?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

10. What times in the day do PLC2 training courses start and end?

Our face-to-face and online courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours.

11. Are course materials provided in a PLC2 training?

All participants of paid courses will receive English training materials in electronic or paper form.

12. Will I receive a certificate upon completion of the PLC2 training course?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

13. Can I pay PLC2 training with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

14. What are the options for payment for PLC2 training?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

15. What is the deadline for payment for PLC2 training?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

16. What are the options for cancelling a PLC2 training?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

17. When will I receive a firm commitment as to whether the PLC2 training course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

18. What is the minimum number of participants for a PLC2 training?

We generally offer courses for 5 or more people. This means that if you would like to book a course at your location, either five people must register or you must pay for five participants, even if fewer people attend.

19. Can I book a PLC2 training course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

20. What language is the PLC2 training course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.

Online Live Training around FPGAs and MPSoCs

Online Live in a Nutshell

Upcoming Online Lives

Online Live Training
around FPGAs and MPSoCs