UVM Testbench Made Easy
Due to the complexity of the UVM library, creating a testbench is a time-consuming task and requires extensive knowledge of the capabilities offered by the library. To support verification engineers in the initial creation of a testbench infrastructure, the UVM framework was developed to create a UVM testbench very quickly. This can be simulated immediately and is adapted to the use case by making changes in some places using application-specific code.
After a short introduction to some UVM classes and expressions, the workshop »UVM Testbench Made Easy« quickly turns to the details of the UVM framework. The course is aimed at verification engineers with no prior UVM knowledge who want to get started using UVM testbenches. The goal of the course is to create a complete UVM testbench using the Siemens EDA UVM Framework (UVMF), which is then supplemented with application-specific code in a few places. The most important UVM building blocks are introduced, providing the basics of how a UVM testbench works, the process of creating instances, and the communication between the UVM components and the DUT. Based on this, the UVM framework verification building blocks and the YAML API are introduced.
Due to accompanying exercises, the course offers in-depth and practice-oriented training. Attendees of the online live training will perform the practical exercises in real time with instructor assistance.
Course language: English
Contact
Michael Schwarz
+49 7664 91313-15
Details
Applicable technologies
NoneRequirements
Knowledge of SystemVerilog and OOP conceptsDuration
2 daysFee (net per person)
€ 1,300Inclusive
Training materialDownloads
Download PDFAgenda
01
Introduction
02
UVM
UVM verification components
UVM transaction interfaces
UVM factory
UVM configuration database
03
UVM Framework
UVMF base classes
UVMF base class package
Introducing the UVMF API
Practical example: creation of a UVM
testbench
Introducing the interface API
Introducing the environment API
Introducing the testbench API
Conclusion
04
References
05
Contact information
06
Exercices
01. Run the UVM example
02. UVM transaction interfaces
03. UVM factory
04. Generating the FPU interface
05. Generating the FPU environment
06. Generating the FPU testbench
07. Completing the testbench
08. Adding another test
Dates
UVM Testbench Made Easy
OL
all year on request
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