Menu

Compact Zynq UltraScale+ MPSoC for the Hardware Designer

Online Live


Workshop

This 3-day course provides both the tool- and architecture- specific aspects necessary for development with the AMD Zynq™ UltraScale+™ MPSoC device. At the beginning, special attention will be paid to the Embedded Design Flow.
The course focuses on embedded hardware development with the AMD Vivado™ tool using the IP Integrator, which also covers software development with the AMD Vitis™ tool.
Then the overall architecture of the Zynq™ Ultra-Scale+™ MPSoC Processing System (PS) is discussed. For the connection of AXI-based IPs in the Programmable Logic (PL) to the Processing System (PS) it is essential to understand the AXI protocol as well as the Interrupt structures. The final section of this course consists of creating and verifying custom IP cores with an AXI-based interface port to the Processing System.

Due to accompanying exercises, the course offers in-depth and practice-oriented training. Attendees of the online live training will perform the practical exercises in real time with instructor assistance.

Course language: English

Portrait von Michael Schwarz

Contact

Michael Schwarz

+49 7664 91313-15

michael.schwarz@plc2.de

Details

Applicable technologies

AMD Zynq™ UltraScale+™ MPSoC and RFSoC,
Kria™ SoMs

Requirements

Basic knowledge of digital system architecture
Basic knowledge in VHDL or Verilog language and C/C++ is an advantage

Duration

3 days

Fee (net per person)

€ 1,900

Inclusive

Training material

Agenda

01

Embedded UltraFast™ design methodology

02

Embedded hardware development

03

Driving the IP integrator tool

04

Driving the Vitis™ tools

05

Zynq™ UltraScale+™ MPSoC architecture

06

Cache coherency management

07

System protection and isolation

08

Introduction to AXI

09

Hardware aspects of interrupts

10

Adding and connecting AXI IP

11

Creating custom AXI IPs

12

Bus functional model simulation

Dates

Compact Zynq UltraScale+ MPSoC for the Hardware Designer

OL

Online

Oct 14, 2024

Book now

Compact Zynq UltraScale+ MPSoC for the Hardware Designer

OL

Online

Feb 03, 2025

Book now

Booking

DE EN

Company

Contact Person

Request / Offer

Billing Address

Billing Person

Participant(s)

Fee

Participant

 

€ 1,900

Course

Compact Zynq UltraScale+ MPSoC for the Hardware Designer_OL

Total fee

€ 1,900

*Required field

Unternehmen

Ansprechpartner:in

Anfrage / Angebot

Rechnungsanschrift

Ansprechpartner:in

Teilnehmer:innnen

Kosten

Teilnehmer:in

 

€ 1,900

Kurs

Compact Zynq UltraScale+ MPSoC for the Hardware Designer_OL

Gesamtbetrag

€ 1,900

*Pflichtfeld

This might also interest you...

Course Format Category Location Duration Date

Professional Zynq UltraScale+ MPSoC

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

5 days

Dec 02, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Professional Zynq UltraScale+ MPSoC

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

5 days

Mar 24, 2025

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Professional Zynq UltraScale+ MPSoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

5 days

Dec 02, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Professional Zynq UltraScale+ MPSoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

5 days

Mar 24, 2025

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Compact Zynq UltraScale+ MPSoC for the Software Designer

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

3 days

Oct 28, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Compact Zynq UltraScale+ MPSoC for the Software Designer

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

3 days

Feb 24, 2025

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Compact Zynq UltraScale+ MPSoC for the Software Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

3 days

Nov 18, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Compact Zynq UltraScale+ MPSoC for the Software Designer

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Stuttgart

3 days

Feb 24, 2025

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

AXI Interface Technology

OL (Online Live)

Connectivity

Online

2 days

Dec 09, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

OL (Online Live)

Connectivity

Online

2 days

Mar 17, 2025

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

WO (Workshop)

Connectivity

Munich

2 days

Nov 28, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

WO (Workshop)

Connectivity

Freiburg

2 days

Mar 17, 2025

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

showing: 1 to 2 (2)

How can we help?

Contact

FAQ

01. Can you help me with reserving the room?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

02. What times in the day do courses start and end?

Our face-to-face courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours. For online courses, the start is also at 9 a.m. (CET/CEST), but they end at 2:30 p.m.. The total course time per day is 4 and a half hours plus breaks.

03. Are course materials provided?

All participants of paid courses will receive English training materials in electronic or paper form.

04. Will I receive a course certificate?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

05. Can I pay with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

06. What are the options for payment?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

07. What is the deadline for payment?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

08. What are the options for cancelling?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

09. When will I receive a firm commitment as to whether the course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

10. How many participants are required for a course to be given/what is the minimum number of participants?

We generally offer courses for 5 or more people. That means that if you would like to book a course at your premises, you need 5 people to register or need to pay the amount for 5 participants, even if fewer people attend.

11. Can I book a course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

12. What language is the course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.