Think Before You Save! - Vivado Design Flow
Webinar
The hardware design flow using the Vivado™ Design Suite includes design run management with high flexibility for the designer. Incremental changes to HDL source files, IP parameterization, physical and timing constraining, and compiler options offer a huge flexibility to manage the build processes of hardware compilations. Therefore, it is particularly important to efficiently organize the build process in incremental steps to achieve fast runtimes and even a good quality (QoR) and a timing closure requirement.
This webinar focuses on design run management by the user to achieve optimal productivity in a step-by-step process. This includes executing a compile build step, assigning physical and timing constraints, validating a step, and taking the next compilation step. For both, a project-based and non-project-based design flow, we can find ways of runtime improvements. A typical problem is seen when a build step does not achieve an improvement as expected, i.e. when more timing paths fail as in a build step before. Here, we want to have the older and the new compilation available, which allows a differential analysis and an alternate decision in continuing on the actual or the older design run build. If we are working purely on source file modifications, we save the file and start the compilation for this next step, which is non-optimal.
In this webinar, we want to show you how 'think before you save' can allow a faster hardware development process using AMD FPGAs and adaptive SoC devices.
Course language: German

Contact
Michael Schwarz
+49 7664 91313-15
Details
Duration
11-12 am CESTDates
Think Before You Save! - Vivado Design Flow
WE
Online
May 21, 2025
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