FPGA Designer (Long Term)

Training Dates March

Mar 10—11, 2025
Mar 17—18, 2025
Mar 26—27, 2025
Apr 01—02, 2025
Apr 14—15, 2025
Apr 28—29, 2025
May 14—15, 2025
May 22—23, 2025

Training Dates September

Sep 09—10, 2025
Sep 22—23, 2025
Sep 29—30, 2025
Oct 13—14, 2025
Oct 27—28, 2025
Nov 10—11, 2025
Nov 19—20, 2025
Nov 26—27, 2025

Session 1: The Vivado™ design system

• Creation of new Vivado™ projects with the new project wizard
• Description of the design types of the Vivado™ IDE
• Generation of DRC reports to detect/isolate design errors
• Using the Vivado™ I/O planning tool to specify FPGA pins
• Exploration and use of synthesis and implementation options and implementation execution
• Presentation of the »baselining« process and its use in optimizing timing specifications
• Generating different synthesis and implementation reports using the Tcl console as well as the Vivado™ GUI
• Use of the »Schematic/Hierarchy Viewer« for sub-component identification and design analysis
• Identification of the influence of implementation on the timing analysis
• Definition of min/max timing parameter processing in the timing analysis report file
• Use of special timing analyzer options to generate special reports
• Specification of I/O timing specifications for »source synchronous« and »system synchronous« applications
• Analysis of the timing reports centering the clock edges in the data eye
• Use of the »Area Constraints« to optimize the design behavior
• Combination of hierarchical viewer, schematic viewer, and timing reports to define optimized area constraints
• Use of »project-based« and »non-project-based« batch instructions for synthesis, implementation, and report file generation

Session 2: FPGA architecture

• Functional description of the 6-Input LUT and the SLICES/CLBS of the 7 series FPGAs
• Specification of the CLB resources and the available SLICE configurations
• Specification of the block RAM, FIFO, and DSP resources
• Specification of the I/O cells and the ISERDES/OSERDES units
• Specification and usage of MMCM/PLL units and clock distribution units
• Definition and usage of the hard IPs for the implementation of the high-performance DDR3 interfaces
• Description of additional hard IP cells of the 7 series FPGAs

Session 3 and 4: VHDL for synthesis

• Overview of the hardware description language VHDL
• Elaboration on the differences between behavioral description and structural description
• Elaboration of the differences between a description of a component for simulation and a synthesis-oriented description of this component
• Use of scalar and composite data types
• Use of serial and concurrent instructions to control the data flow
• Description of basic components using common VHDL constructs
• Finite State Machines (FSM)
• Description of RAM/ROM data structures
• Introduction to VHDL simulation
• Definition of basic rules for modeling components

Session 5: VHDL for simulation

• Description and use of VHDL testbenches
• Use of existing packages for the description of reusable functions
• Creation of own packages for the description of reusable functions
• Creation of self-testing testbenches
• Description of realistic simulation models
• Use of file I/O for dynamic storage of simulation data
• Use of file I/O for the generation of input test data
• Use of parameters (generics) for the description of reusable functions and components

Session 6 and 7: Development process and FPGA design techniques

• Definition of the »UltraFast™ Design Methodology«
• Identification of key parameters to optimize timing / area specifications
• Definition of a correctly specified FPGA design
• Optimization of the VHDL description to increase the required FPGA resources’ efficiency and achieve the timing specifications, respectively.
• Recommended use of RESET structures
• Use of different synchronization techniques to avoid metastability and to optimize hardware verification
• Use of the »Vivado™ Clock Interaction« report
• Definition of the methodology for timing optimization (»Timing Closure«)
• Use of the AMD XDC constraints for the description of invalid paths, paths with defined exceptions, or paths that can be traversed in multiple clocks (timing exceptions, false paths, multi-cycle path constraints)
• Use of static timing analysis to analyze delay times
• Use of special XDC I/O constraints for specification of external components
• Description of different synthesis options to improve design performance

Session 8: FPGA debugging and logic analyzer

• Specification and use of the Vivado™ IDE Debug Cores
• Efficient use of the Vivado™ Logic Analyzer
• Implementation of the Vivado™ Debug Cores using netlist insertion or instantiation in the VHDL description
• Hints for the effective use of internal test points
• Optimization of design performance when using Vivado™ Debug Cores
• Description of different methods for data acquisition, including data storage, scripting, and specification of special trigger events