Development
Tools & Methodology

FPGA Designer (Long Term)

Long Term Education

PLC2 turns engineers and technicians into FPGA experts. Our three-month advanced training program imparts the know-how for the entire AMD embedded development process - on the job, alongside work. At the end of the training course, participants are able to develop FPGAs independently.

The concept of long-term education is based on step-by-step training for participants. Starting with the architecture as well as the basics of FPGA circuit technology, the agenda includes the complete FPGA development process. The course program consists of a coordinated combination of theory and practice. Participants learn to design and implement their own FPGA designs.

The training is divided into eight face-to-face units at PLC2 on-site, optionally online, with two days each. Between the attendance sessions, there is the possibility to repeat and deepen the knowledge with training material and its own evaluation board.

Theoretical units are supplemented by exercises and own FPGA developments. Exercises and self-directed FPGA developments are a central part of the training. Of course, our trainers also provide support between the classroom sessions and are happy to answer questions.

Course language: German (English possible on request)

Book workshop

Contact

Michael Schwarz

+49 7664 91313-15

michael.schwarz@plc2.de

Details

Applicable technologies

AMD FPGAs

Requirements

Work experience in the field of electronics

Duration

8 dates of 2 days each

Fee (net per person)

€ 8,400

Inclusive

AMD evaluation board with example solutions
Training material
Beverages during breaks
Lunch

Agenda

Training Dates March

Mar 07—08, 2024
Mar 18—19, 2024
Mar 26—27, 2024
Apr 02—03, 2024
Apr 17—18, 2024
Apr 29—30, 2024
May 06—07, 2024
May 15—16, 2024

Training Dates September

Sep 10—11, 2024
Sep 23—24, 2024
Oct 07—08, 2024
Oct 16—17, 2024
Oct 23—24, 2024
Nov 11—12, 2024
Nov 18—19, 2024
Nov 27—28, 2024

Session 1: The Vivado™ design system

• Creation of new Vivado™ projects with the new project wizard
• Description of the design types of the Vivado™ IDE
• Generation of DRC reports to detect/isolate design errors
• Using the Vivado™ I/O planning tool to specify FPGA pins
• Exploration and use of synthesis and implementation options and implementation execution
• Presentation of the »baselining« process and its use in optimizing timing specifications
• Generating different synthesis and implementation reports using the Tcl console as well as the Vivado™ GUI
• Use of the »Schematic/Hierarchy Viewer« for sub-component identification and design analysis
• Identification of the influence of implementation on the timing analysis
• Definition of min/max timing parameter processing in the timing analysis report file
• Use of special timing analyzer options to generate special reports
• Specification of I/O timing specifications for »source synchronous« and »system synchronous« applications
• Analysis of the timing reports centering the clock edges in the data eye
• Use of the »Area Constraints« to optimize the design behavior
• Combination of hierarchical viewer, schematic viewer, and timing reports to define optimized area constraints
• Use of »project-based« and »non-project-based« batch instructions for synthesis, implementation, and report file generation

Session 2: FPGA architecture

• Functional description of the 6-Input LUT and the SLICES/CLBS of the 7 series FPGAs
• Specification of the CLB resources and the available SLICE configurations
• Specification of the block RAM, FIFO, and DSP resources
• Specification of the I/O cells and the ISERDES/OSERDES units
• Specification and usage of MMCM/PLL units and clock distribution units
• Definition and usage of the hard IPs for the implementation of the high-performance DDR3 interfaces
• Description of additional hard IP cells of the 7 series FPGAs

Session 3 and 4: VHDL for synthesis

• Overview of the hardware description language VHDL
• Elaboration on the differences between behavioral description and structural description
• Elaboration of the differences between a description of a component for simulation and a synthesis-oriented description of this component
• Use of scalar and composite data types
• Use of serial and concurrent instructions to control the data flow
• Description of basic components using common VHDL constructs
• Finite State Machines (FSM)
• Description of RAM/ROM data structures
• Introduction to VHDL simulation
• Definition of basic rules for modeling components

Session 5: VHDL for simulation

• Description and use of VHDL testbenches
• Use of existing packages for the description of reusable functions
• Creation of own packages for the description of reusable functions
• Creation of self-testing testbenches
• Description of realistic simulation models
• Use of file I/O for dynamic storage of simulation data
• Use of file I/O for the generation of input test data
• Use of parameters (generics) for the description of reusable functions and components

Session 6 and 7: Development process and FPGA design techniques

• Definition of the »UltraFast™ Design Methodology«
• Identification of key parameters to optimize timing / area specifications
• Definition of a correctly specified FPGA design
• Optimization of the VHDL description to increase the required FPGA resources’ efficiency and achieve the timing specifications, respectively.
• Recommended use of RESET structures
• Use of different synchronization techniques to avoid metastability and to optimize hardware verification
• Use of the »Vivado™ Clock Interaction« report
• Definition of the methodology for timing optimization (»Timing Closure«)
• Use of the AMD XDC constraints for the description of invalid paths, paths with defined exceptions, or paths that can be traversed in multiple clocks (timing exceptions, false paths, multi-cycle path constraints)
• Use of static timing analysis to analyze delay times
• Use of special XDC I/O constraints for specification of external components
• Description of different synthesis options to improve design performance

Session 8: FPGA debugging and logic analyzer

• Specification and use of the Vivado™ IDE Debug Cores
• Efficient use of the Vivado™ Logic Analyzer
• Implementation of the Vivado™ Debug Cores using netlist insertion or instantiation in the VHDL description
• Hints for the effective use of internal test points
• Optimization of design performance when using Vivado™ Debug Cores
• Description of different methods for data acquisition, including data storage, scripting, and specification of special trigger events

Dates

FPGA Designer (Long Term)

Freiburg

Sep 10, 2024

Book now

Available formats for this training

FPGA Designer (Long Term)

8 dates of 2 days each

€ 8,400

Long Term Education

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How can we help?

Contact

Call PLC2

+49 7664 91313-15

Send an e-mail

michael.schwarz@plc2.de

FAQ

01. Can you help me with reserving the room?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

02. What times in the day do courses start and end?

Our face-to-face courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours. For online courses, the start is also at 9 a.m. (CET/CEST), but they end at 2:30 p.m.. The total course time per day is 4 and a half hours plus breaks.

03. Are course materials provided?

All participants of paid courses will receive English training materials in electronic or paper form.

04. Will I receive a course certificate?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

05. Can I pay with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

06. What are the options for payment?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

07. What is the deadline for payment?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

08. What are the options for cancelling?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

09. When will I receive a firm commitment as to whether the course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

10. How many participants are required for a course to be given/what is the minimum number of participants?

We generally offer courses for 5 or more people. That means that if you would like to book a course at your premises, you need 5 people to register or need to pay the amount for 5 participants, even if fewer people attend.

11. Can I book a course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

12. What language is the course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.