Understanding Versal: Scalar Engines - The Processing System
Webinar
This session will focus on the Processing System in Versal including the ARM APU, the ARM RPU, and Xilinx microcontrollers. The scalar engines include processing units based on sequential processing while other Versal engines support parallel processing. We describe the Cortex-A72 APU architecture, the Cortex-R5F architecture the Xilinx Platform manager (PMC), and the processing system manager. Dedicated peripheral and memory i/o pins can be configured with the processing system. The power domains in the PS provide a topology to fulfill safety requirements. For asynchronous processing and inter-processor communication, interrupt management is needed. Therefore, the system interrupts controllers will be described as well in this webinar.
Course language: English
Contact
Michael Schwarz
+49 7664 91313-15
Details
Duration
1 hourDates
Understanding Versal: Scalar Engines - The Processing System
WE
Online
on demand
Available formats for this training
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