AMD (Adaptive) SoC, MPSoC & FPGA Architecture

Compact FPGA 7 Series

Workshop

Online Live

The PLC2 workshop »Compact FPGA 7 Series« teaches the first-time or recurring user the way, the FPGA building blocks of the 7 series devices of AMD FPGAs work and how they can be used most effectively.

The emphasis of this workshop is put on the thorough discussion of the common architectural building blocks of the 7 series devices. After an overview, detailed explanations are given to the functional blocks such as e.g., Configurable Logic Blocks (CLB), I/O Blocks (IOB) for system- or source synchronous data transmission in single or double data rate mode, DSP, etc. Due to its crucial role in an FPGA design, special attention is given to the clocking resources and clock structure. Finally, dedicated hardware resources (such as, e.g., GTP and PCIe®) will briefly be introduced.
Moreover, suitable coding techniques get explained throughout the class to allow synthesis to produce the best possible implementation results based on the target device’s resources. Exercises help to reinforce the learning process.
Neither hardware description languages like VHDL nor global implementation strategies are covered in this class. Please refer to PLC2 workshops like »Compact VHDL for Synthesis«, »Compact VHDL for Simulation« or »Professional VHDL«.

Due to accompanying exercises, the course offers in-depth and practice-oriented training.

Course language: German (English possible on request)

Book workshop

Contact

Michael Schwarz

+49 7664 91313-15

michael.schwarz@plc2.de

Details

Applicable technologies

AMD FPGAs

Requirements

Basic knowledge in VHDL and digital design techniques
Basic knowledge of the AMD design tool flow

Duration

2 days

Fee (net per person)

€ 1,700

Inclusive

Training material
Plus beverages during breaks
Lunch

Agenda

CLB architecture

CLB structure and routing
Slice resources
Distributed RAM/SRL
Using slice resources

Slice flip-flops

Control sets
Designing resets
Other reset considerations

Memory resources

Block RAM capabilities
FIFO capabilities
Using block RAM resources

DSP resources

7 Series FPGA DSP Slice
Pre-Adder and dynamic pipeline control Advantages
IP support and inference

I/O resources

SelectIO™ electrical resources
SelectIO™ logical resources
Power savings
Using SelectIO™ resources

Clocking resources

Clock networks and buffers
Clock management tile
Usage models
Using clock resources

Memory controller

Phaser and I/O FIFOs
Memory controller
Memory Interface Generator (MIG)

Dedicated hardware

Serial Gigabit transceivers
PCI Express® technology interface
XADC

HDL coding techniques

Hierarchy
Control sets
Synthesis options

Dates

Compact FPGA 7 Series

on request all year tbd

Book now

Available formats for this training

Compact FPGA 7 Series

2 days

€ 1,700

Workshop

Compact FPGA 7 Series

2 days

€ 1,300

Online Live

This might also interest you...

Course	Format	Category	Location	Duration	Date
Professional FPGA	PW (Power Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Frankfurt / Main	5 days	Feb 17, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA	PW (Power Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Stuttgart	5 days	May 12, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA	PW (Power Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Freiburg	5 days	Jul 14, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA	PW (Power Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Munich	5 days	Oct 20, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	5 days	Feb 17, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	5 days	May 12, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	5 days	Jul 14, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	5 days	Oct 20, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Compact UltraScale/UltraScale+	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	2 days	Mar 05, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	2 days	Jun 10, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	2 days	Sep 25, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+	OL (Online Live)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Online	2 days	Nov 24, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Munich	2 days	Mar 05, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Freiburg	2 days	Jun 10, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Frankfurt / Main	2 days	Sep 25, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact UltraScale/UltraScale+	WO (Workshop)	AMD (Adaptive) SoC, MPSoC & FPGA Architecture	Stuttgart	2 days	Nov 24, 2025	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP Ultrascale Ultrascale+ IO
Compact Timing Constraints and Analysis	OL (Online Live)	Development Tools & Methodology	Online	3 days	Feb 19, 2025	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis	OL (Online Live)	Development Tools & Methodology	Online	3 days	Jun 25, 2025	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 17, 2025	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 19, 2025	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis	WO (Workshop)	Development Tools & Methodology	Freiburg	3 days	Feb 19, 2025	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	Jun 25, 2025	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Sep 17, 2025	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis	WO (Workshop)	Development Tools & Methodology	Munich	3 days	Nov 19, 2025	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Professional FPGA Circuit Design Technique	OL (Online Live)	Development Tools & Methodology	Online	5 days	Feb 10, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique	OL (Online Live)	Development Tools & Methodology	Online	5 days	Apr 07, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique	OL (Online Live)	Development Tools & Methodology	Online	5 days	Jul 07, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique	OL (Online Live)	Development Tools & Methodology	Online	5 days	Nov 03, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Feb 10, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Apr 07, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Jul 07, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Nov 03, 2025	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional Vivado	OL (Online Live)	Development Tools & Methodology	Online	5 days	Mar 10, 2025	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	OL (Online Live)	Development Tools & Methodology	Online	5 days	Jul 07, 2025	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	OL (Online Live)	Development Tools & Methodology	Online	5 days	Oct 20, 2025	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	OL (Online Live)	Development Tools & Methodology	Online	5 days	Dec 01, 2025	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Mar 10, 2025	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	PW (Power Workshop)	Development Tools & Methodology	Frankfurt / Main	5 days	Jul 07, 2025	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Oct 20, 2025	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	PW (Power Workshop)	Development Tools & Methodology	Frankfurt / Main	5 days	Dec 01, 2025	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Items per page 10 25 50 100 prev next showing: 1 to 2 (2)

How can we help?

Contact

Call PLC2

+49 7664 91313-15

Send an e-mail

michael.schwarz@plc2.de

FAQ

01. Can you help me with reserving the room?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

02. What times in the day do courses start and end?

Our face-to-face and online courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours.

03. Are course materials provided?

All participants of paid courses will receive English training materials in electronic or paper form.

04. Will I receive a course certificate?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

05. Can I pay with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

06. What are the options for payment?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

07. What is the deadline for payment?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

08. What are the options for cancelling?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

09. When will I receive a firm commitment as to whether the course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

10. How many participants are required for a course to be given/what is the minimum number of participants?

We generally offer courses for 5 or more people. That means that if you would like to book a course at your premises, you need 5 people to register or need to pay the amount for 5 participants, even if fewer people attend.

11. Can I book a course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

12. What language is the course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.