Menu

Embedded Designer (Long Term)

Long Term Education


PLC2 turns engineers and technicians into FPGA experts. Our three-month advanced training program imparts the know how for the entire AMD embedded development process - on the job, alongside work. At the end of the training course, participants are able to develop designs for AMD Zynq™ 7000 SoC and Zynq™ Ultrascale+™ MPSoC independently.

The concept of our PLC2 Long Term Education is based on step by step training for participants. Starting with the architecture of the Zynq™ SoC and MPSoC devices as well as the Vivado™ tool flow, the underlying agenda includes the complete AMD embedded development process. The course program consists of a coordinated combination of theory and practice. Participants learn to design and implement their own SoC/MPSoC designs. The training is divided into eight face to face units at PLC2 on-site, with two days each. Between the attendance sessions, there is the possibility to repeat and deepen the knowledge with training material and its own evaluation board.

Theoretical units are supplemented by exercises and own developments. Exercises and self-directed developments are a central part of the training. Of course, our trainers also provide support between the classroom sessions and are happy to answer questions.

Course language: German (English possible on request)

Portrait von Michael Schwarz

Contact

Michael Schwarz

+49 7664 91313-15

michael.schwarz@plc2.de

Details

Applicable technologies

AMD FPGAs and adaptive SoCs,
Kria™ SoMs

Requirements

Work experience in the
field of electronics

Duration

8 dates of 2 days each

Fee (net per person)

€ 8,400

Inclusive

AMD evaluation board with example solutions
Training material
Beverages during breaks
Lunch

Agenda

01

Training Dates April

Apr 03—04, 2024
Apr 15—16, 2024
May 02—03, 2024
May 13—14, 2024
May 22—23, 2024
June 03—04, 2024
June 12—13, 2024
June 26—27, 2023

02

Training Dates October

Oct 01—02, 2024
Oct 14—15, 2024
Oct 21—22, 2024
Nov 06—07, 2024
Nov 18—19, 2024
Nov 25—26, 2024
Dec 02—03, 2024
Dec 11—12, 2024

03

Session 1: AMD embedded design flow

• Understanding of a methodical embedded development – the AMD UltraFast™ methodology
• An introduction for software designers to programmable logic architecture (FPGA)
• Management of hardware design with Arm® and AMD processors in Vivado™ tool suite
• Design entry with IP integrator (IPI) of processors, memory, and peripherals
• Control of hardware implementation, run, and constraints management in Vivado™
• Understanding of report analysis: flow, timing closure, utilization, power consumption
• Vitis™ design - Eclipse-based AMD software project management and embedded software design flow
• The methodology of migration of IPs in Vivado™ and user IP version management
• Design maintenance of software projects in case of hardware changes with AMD Vitis™
• The methodology of migration of Eclipse/SDK projects to Vitis™
• Application of hardware based JTAG debugging with Vitis™ wizard
• Introduction to boot loading, creating, and running boot images
• The complete embedded design flow on a reference example design
• The AMD TCL consoles for Vivado™ and Vitis™ projects

04

Session 2: Processors, SoC, and MPSoC architectures

• Introduction to MPSoC architectures
• Introduction to the AMD Zynq™ UltraScale+™ MPSoC architecture
• Comparisons with Zynq™ SoC architectures
• Overview of Arm® processor architectures APU/RPU/PMU
• Application type processor APU - Cortex®™-A53
• Arm® realtime type processor RPU - Cortex®-R5
• Neon™ engines for SIMD technology and floating point support
• 32 bit and/or 64 bit processing with Cortex®-A53
• AMD MicroBlaze™ processor architecture
• Compare AMD MicroBlaze™ vs. Arm® MPU Cortex®-M1/M3
• Interrupt management and interrupt controller
• Porting and migration in case of processor change
• Bootloader creation and boot image generation
• Coherence and cache management in software and hardware
• Safety and isolation of accesses with Sharing Memory and Sharing Peripherals
• Secure management and Arm® TrustZone®
• Power islands in Zynq™ UltraScale+™ MPSoC

05

Session 3 AXI based IP development

• AMBA® bus standards: APB, AHP, AXI3, AXI4
• AXI-based connectivity
• AXI variants and timing diagrams
• AXI PS/PL port types and configurations
• Coherence management and AXI interconnects: ACP, ACE, and HPC types
• Creation of embedded user peripherals with AXI interface
• IP validation: BFM simulation, system simulation, and hardware testing
• VIP: AMD Verification IP for simulation of AXI peripherals
• Unit tests with AXI traffic generator and AXI performance monitor IPs
• Optimization of data throughput and latency as well as analysis
• Integration of DMA and data mover IPs for data packet transfers
• Architecture of multiport accesses at the DDRAM controller
• QoS: arbitration, prioritization of port accesses to DDRAM memory
• AXI-based system performance modeling
• Integration of an accelerator IP from Vivado™ HLS

06

Session 4: Embedded software design

• Vitis™ - OS and domain management
• The BareMetal-based operating system
• Application development with Vitis™
• Application Programming Interfaces (API) of the AMD libraries
• Timer programming, timer in PS and PL
• Software driver and driver layers in Vitis™
• AMD software stacks in Vitis™
• Interrupt management and creation of interrupt handlers
• The creation of a software driver and integration into the BSP
• An overview of power management and platform management
• Overview and selection criteria of embedded operating systems
• Introduction to boot mechanisms

07

Session 5: Validation methodologies

• Debugging, simulation, and emulation
• An introduction to the Arm® CoreSight™ architecture
• Debug Flow in Vitis™ with GDB
• Debug Flow in Vitis™ with System Debugger (à Intel System Debugger?)
• Console-based debugging (xsct/xsdb/hsi)
• Debugging an interrupt handler application
• An introduction to QEMU emulation
• Co-debugging of hardware and software
• Single-Processor and Multi-Processor debugging
• QEMU Co-Simulation: Emulation plus HDL simulation of the PL architecture
• Cross-Triggering: CPU cores and PL integrated logic analysis
• MicroBlaze™ system simulation
• Testing with JTAG based measurement, memory dump, and injection
• FSBL creation, analysis, and FSBL debugging

08

Session 6: Embedded systems integration

• SMP and AMP support
• The components of a Linux operating system
• Application development with PetaLinux
• The FreeRTOS™ based operating system
• The OpenAMP framework for message inter-communication
• Introduction to platform management and PMU controller
• IPI Protocol of the platform manager (PMU)
• Platform boot and power management
• Platform management unit in Zynq™ UltraScale+™ MPSoC
• Describe the power islands
• Managing power for other processors
• Power management and use of the PMU firmware library
• Extending the PMU firmware with user tasks
• Non-secure and secure boot management
• FSBL customization and debugging
• The scenario and analysis of a failed Linux boot

09

Session 7: PetaLinux tools and development

• An introduction to AMD PetaLinux
• Application development for Linux OS
• The configuration of an OS Linux for the APU system
• Configuration of Linux kernel and Linux file system
• The PetaLinux build flow
• Creating a user peripheral with software drivers
• The Linux-based operating system
• Networking and TCP-IP
• Userspace I/O and loadable kernel modules
• Linux device drivers overview
• PetaLinux image booting methods
• Configuration of the rootfs file system
• Custom driver development for custom IPs
• Overview of Yocto builds and Yocto in PetaLinux
• An overview of Yocto builds and comparison with PetaLinux flow

10

Session 8: Linux drivers

• An introduction Linux basics for driver development
• Driver support from uBoot
• Device tree overlay management
• Fundamental basics of Linux driver modules
• Character driver - the preferred module for user peripheral drivers
• Driver for Embedded Linux with the UIO framework
• Platform driver and device tree management (DTS/DTB)
• Linux driver API for timers, threads, work queues, and more
• Control mechanisms and debugging of a Linux driver
• Linux interrupt mechanisms

Dates

Embedded Designer (Long Term)

LT

Freiburg

Oct 01, 2024

Book now

Booking

DE EN

Company

Contact Person

Request / Offer

Billing Address

Billing Person

Participant(s)

Fee

Participant

 

€ 8,400

Course

Embedded Designer_LT

Total fee

€ 8,400

*Required field

Unternehmen

Ansprechpartner:in

Anfrage / Angebot

Rechnungsanschrift

Ansprechpartner:in

Teilnehmer:innnen

Kosten

Teilnehmer:in

 

€ 8,400

Kurs

Embedded Designer_LT

Gesamtbetrag

€ 8,400

*Pflichtfeld

This might also interest you...

Course Format Category Location Duration Date

Professional Zynq UltraScale+ MPSoC

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

5 days

Dec 02, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Professional Zynq UltraScale+ MPSoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Freiburg

5 days

Sep 16, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Professional Zynq UltraScale+ MPSoC

PW (Power Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Frankfurt / Main

5 days

Dec 02, 2024

Info

Embedded Architecture Vivado Vitis MPSoC Cortex-A53 Cortex-R5 Processor Cache Coherency Hypervisor PetaLinux Protection PCIe PS PMU Power IP-Integrator AXI ACE Vitis

Compact Vitis for the Software Designer

OL (Online Live)

Development
Tools & Methodology

Online

3 days

Dec 16, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging

Compact Vitis for the Software Designer

WO (Workshop)

Development
Tools & Methodology

Berlin

3 days

Sep 17, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging

Compact Vitis for the Software Designer

WO (Workshop)

Development
Tools & Methodology

Munich

3 days

Dec 16, 2024

Info

Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging

AXI Interface Technology

OL (Online Live)

Connectivity

Online

2 days

Aug 01, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

OL (Online Live)

Connectivity

Online

2 days

Dec 09, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

WO (Workshop)

Connectivity

Berlin

2 days

Sep 09, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

WO (Workshop)

Connectivity

Munich

2 days

Nov 28, 2024

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

Embedded Design with PetaLinux Tools

OL (Online Live)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Online

2 days

Nov 28, 2024

Info

Embedded Linux PetaLinux build rootfs kernel driver layer DeviceTree Device-Tree Boot

Embedded Design with PetaLinux Tools

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Berlin

2 days

Sep 11, 2024

Info

Embedded Linux PetaLinux build rootfs kernel driver layer DeviceTree Device-Tree Boot

Embedded Design with PetaLinux Tools

WO (Workshop)

Embedded for AMD (Adaptive) SoCs & MPSoCs

Munich

2 days

Nov 28, 2024

Info

Embedded Linux PetaLinux build rootfs kernel driver layer DeviceTree Device-Tree Boot

showing: 1 to 2 (2)

How can we help?

Contact

FAQ

01. Can you help me with reserving the room?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

02. What times in the day do courses start and end?

Our face-to-face courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours. For online courses, the start is also at 9 a.m. (CET/CEST), but they end at 2:30 p.m.. The total course time per day is 4 and a half hours plus breaks.

03. Are course materials provided?

All participants of paid courses will receive English training materials in electronic or paper form.

04. Will I receive a course certificate?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

05. Can I pay with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

06. What are the options for payment?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

07. What is the deadline for payment?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

08. What are the options for cancelling?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

09. When will I receive a firm commitment as to whether the course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

10. How many participants are required for a course to be given/what is the minimum number of participants?

We generally offer courses for 5 or more people. That means that if you would like to book a course at your premises, you need 5 people to register or need to pay the amount for 5 participants, even if fewer people attend.

11. Can I book a course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

12. What language is the course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.