Embedded for AMD (Adaptive) SoCs & MPSoCs

All about Memories in Adaptive SoCs

Webinar

This webinar gives you a structural and methodical overview how memory resources are available and how they can be used in hardware and software programming methodologies. Here, we will focus on memory resources used for the run-time environment, not for the boot process. Programmable logic or adaptable engines provide three types of local memories and a variety of memory controllers for external memories like DRAMs or SRAMs. In the processing, local memory and tight-coupled memories are available and most important memory controllers for static and dynamic external RAMs on-chip or off-chip. For the embedded and application developer it’s very important to manage the memory resources in a best way to achieve their specification like high data rate throughput, minimum latencies, data type organization, multi-port, and arbitrated shared accesses, error correction, protection or coherency management and software driver support. This can be a challenge as this depends on the design specification, the expertise of the developers, the technology capabilities, responsibilities in a team-based design and the AMD tool flows which are used.
This webinar gives a structural and methodical overview for embedded and system designers using AMD SoC and Adaptive SoC devices.

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Contact

Michael Schwarz

+49 7664 91313-15

michael.schwarz@plc2.de

Details

Duration

11-12 am CEST

Dates

All about Memories in Adaptive SoCs

Online

May 28, 2024

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Available formats for this training

All about Memories in Adaptive SoCs

11-12 am CEST

€ 0

Webinar

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+49 7664 91313-15

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michael.schwarz@plc2.de

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