PLC2 Training category Tools & Methodology

Development
Tools & Methodology

The HDL-based development method simplifies the development cycle, but this requires the developer to have good knowledge of digital circuit design. It is not enough to know how to implement combinational and sequential circuits, it is very important to know how to implement your design in the FPGA architecture to maximize benefits in size, power and performance.
The PLC2 training courses in the »tools and methodology« category help developers use and apply the development tools for these latest technologies.

Upcoming Trainings

Course	Format	Category	Location	Duration	Date
Compact Timing Constraints and Analysis	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	Jun 24, 2026	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Sep 23, 2026	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis	WO (Workshop)	Development Tools & Methodology	Munich	3 days	Nov 18, 2026	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Jun 24, 2026	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 23, 2026	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Compact Timing Constraints and Analysis \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 18, 2026	Info Vivado Timing Constraints Tool STA TCL XDC static timing analysis timing closure timing summary clock interaction
Professional FPGA Circuit Design Technique	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Apr 13, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Jul 06, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Nov 02, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Apr 13, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Jul 06, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Professional FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Nov 02, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Yocto Embedded Linux Development	WO (Workshop)	Development Tools & Methodology	Munich	2 days	Jun 01, 2026	Info Yocto, Linux, PetaLinux, Open-Source, Zynq, Kernel, rootfs, device driver
Yocto Embedded Linux Development	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	2 days	Sep 14, 2026	Info Yocto, Linux, PetaLinux, Open-Source, Zynq, Kernel, rootfs, device driver
Yocto Embedded Linux Development	WO (Workshop)	Development Tools & Methodology	Freiburg	2 days	Nov 09, 2026	Info Yocto, Linux, PetaLinux, Open-Source, Zynq, Kernel, rootfs, device driver
Scripting the AMD Hardware Design Flow Using Vivado	WO (Workshop)	Development Tools & Methodology	Freiburg	3 days	Mar 23, 2026	Info
Scripting the AMD Hardware Design Flow Using Vivado	WO (Workshop)	Development Tools & Methodology	Munich	3 days	Jun 01, 2026	Info
Scripting the AMD Hardware Design Flow Using Vivado	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	Sep 16, 2026	Info
Scripting the AMD Hardware Design Flow Using Vivado	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	Nov 23, 2026	Info
Scripting the AMD Hardware Design Flow Using Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Mar 23, 2026	Info
Scripting the AMD Hardware Design Flow Using Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Jun 01, 2026	Info
Scripting the AMD Hardware Design Flow Using Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 16, 2026	Info
Scripting the AMD Hardware Design Flow Using Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 23, 2026	Info
Advanced Vivado	WO (Workshop)	Development Tools & Methodology	Freiburg	3 days	Apr 15, 2026	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Jul 06, 2026	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	Oct 14, 2026	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Apr 15, 2026	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Jul 06, 2026	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
Advanced Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Oct 14, 2026	Info Tools and Methodology AMD Advanced Vivado design suite tool hardware debugging debug tool tools TCL scripting FPGAs adaptive SoCs SoC VHDL Verilog
FPGA Designer (Long Term)	LT (Long Term Education)	Development Tools & Methodology	Freiburg	8 dates of 2 days each	Sep 15, 2026	Info
Compact Vivado Design Suite Tool Flow	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	2 days	Jun 22, 2026	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
Compact Vivado Design Suite Tool Flow	WO (Workshop)	Development Tools & Methodology	Stuttgart	2 days	Sep 21, 2026	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
Compact Vivado Design Suite Tool Flow	WO (Workshop)	Development Tools & Methodology	Munich	2 days	Nov 16, 2026	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
Compact Vivado Design Suite Tool Flow \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Jun 22, 2026	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
Compact Vivado Design Suite Tool Flow \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Sep 21, 2026	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
Compact Vivado Design Suite Tool Flow \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Nov 16, 2026	Info Vivado FPGA Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL XDC project mode non-project-mode
FPGA Circuit Design Technique	SE (Seminar)	Development Tools & Methodology	Freiburg	1 day	Sep 30, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung IP Core
Professional Vivado	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Mar 23, 2026	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	PW (Power Workshop)	Development Tools & Methodology	Frankfurt / Main	5 days	Jul 27, 2026	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Oct 05, 2026	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado	PW (Power Workshop)	Development Tools & Methodology	Frankfurt / Main	5 days	Dec 14, 2026	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Mar 23, 2026	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Jul 27, 2026	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Oct 05, 2026	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Dec 14, 2026	Info Vivado Clock Interaction Tool Synthesis Implementation Blockdiagram Blockdesign IPI IP Core Integrator Design Flow Simulation Xsim Simulator TCL FPGA XDC project mode non-project-mode timing constraints STA static timing analysis timing closure timing summary
Professional Vitis	PW (Power Workshop)	Development Tools & Methodology	Stuttgart	5 days	Jun 15, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT
Professional Vitis	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	Aug 03, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT
Professional Vitis	PW (Power Workshop)	Development Tools & Methodology	Berlin	5 days	Nov 09, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT
Professional Vitis \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Jun 15, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT
Professional Vitis \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Aug 03, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT
Professional Vitis \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Nov 09, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging Profiling Acceleration XRT
Git for EDA Tool Flows	WO (Workshop)	Development Tools & Methodology	Munich	3 days	Jun 01, 2026	Info Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging
Git for EDA Tool Flows	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	Sep 01, 2026	Info Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging
Git for EDA Tool Flows	WO (Workshop)	Development Tools & Methodology	Freiburg	3 days	Dec 01, 2026	Info Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging
Git for EDA Tool Flows \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Jun 01, 2026	Info Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging
Git for EDA Tool Flows \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 01, 2026	Info Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging
Git for EDA Tool Flows \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Dec 01, 2026	Info Git Tools Versioning Version Control Scripting Script GitLab SmartGit Branching Merging
FPGA Power Optimization	WO (Workshop)	Development Tools & Methodology		2 days	all year on request	Info FPGA Power Vivado Kintex XCE clocking
FPGA Power Optimization \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	all year on request	Info FPGA Power Vivado Kintex XCE clocking
Easy Start FPGA Vivado	ES (Easy Start)	Development Tools & Methodology	Freiburg	2 days	May 04, 2026	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Easy Start FPGA Vivado	ES (Easy Start)	Development Tools & Methodology	Stuttgart	2 days	Aug 10, 2026	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Easy Start FPGA Vivado	ES (Easy Start)	Development Tools & Methodology	Frankfurt / Main	2 days	Nov 23, 2026	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Easy Start FPGA Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	May 04, 2026	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Easy Start FPGA Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Aug 10, 2026	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Easy Start FPGA Vivado \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Nov 23, 2026	Info FPGA VHDL Introduction Beginner Overview FPGA Ressources Synthese Software C C++ Einführung Einstieg Vivado IP Core Introduction Synthesis Simulation State Machine Architecture Design Flow easy start
Dynamic Function eXchange (DFX)	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	2 days	Apr 27, 2026	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Dynamic Function eXchange (DFX)	WO (Workshop)	Development Tools & Methodology	Stuttgart	2 days	Jul 09, 2026	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Dynamic Function eXchange (DFX)	WO (Workshop)	Development Tools & Methodology	Freiburg	2 days	Oct 12, 2026	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Dynamic Function eXchange (DFX) \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Apr 27, 2026	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Dynamic Function eXchange (DFX) \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Jul 09, 2026	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Dynamic Function eXchange (DFX) \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Oct 12, 2026	Info FPGA DFX Vivado partial configuration functions Black Box Floorplaning
Debugging Techniques Using the Vivado Logic Analyzer	WO (Workshop)	Development Tools & Methodology	Freiburg	2 days	Jun 17, 2026	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Debugging Techniques Using the Vivado Logic Analyzer	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	2 days	Sep 17, 2026	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Debugging Techniques Using the Vivado Logic Analyzer	WO (Workshop)	Development Tools & Methodology	Munich	2 days	Dec 01, 2026	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Debugging Techniques Using the Vivado Logic Analyzer \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Jun 17, 2026	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Debugging Techniques Using the Vivado Logic Analyzer \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Sep 17, 2026	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Debugging Techniques Using the Vivado Logic Analyzer \| Online	OL (Online Live)	Development Tools & Methodology	Online	2 days	Dec 01, 2026	Info Vivado Debug Tool ILA Debugging Scope VIO Probe probing bug analyze Vivado Blockdesign IPI IP Core Integrator Synthesis Implementation
Continuous Integration for EDA Tools	PW (Power Workshop)	Development Tools & Methodology	Freiburg	5 days	May 04, 2026	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Continuous Integration for EDA Tools	PW (Power Workshop)	Development Tools & Methodology	Frankfurt / Main	5 days	Jul 27, 2026	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Continuous Integration for EDA Tools	PW (Power Workshop)	Development Tools & Methodology	Berlin	5 days	Oct 05, 2026	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Continuous Integration for EDA Tools \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	May 04, 2026	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Continuous Integration for EDA Tools \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Jul 27, 2026	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Continuous Integration for EDA Tools \| Online	OL (Online Live)	Development Tools & Methodology	Online	5 days	Oct 05, 2026	Info FPGA Git Tools Versioning Version Control Scripting Script GitLab Docker Vivado Vitis Riviera-PRO GHDL
Compact Vitis for the Software Designer	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	May 11, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
Compact Vitis for the Software Designer	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	Sep 07, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
Compact Vitis for the Software Designer	WO (Workshop)	Development Tools & Methodology	Munich	3 days	Dec 16, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
Compact Vitis for the Software Designer \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	May 11, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
Compact Vitis for the Software Designer \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 07, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
Compact Vitis for the Software Designer \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Dec 16, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Boot Bootflow elf c/c++ Standalone Debugging
Compact Vitis for Acceleration	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	May 04, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging
Compact Vitis for Acceleration	WO (Workshop)	Development Tools & Methodology	Freiburg	3 days	Aug 17, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging
Compact Vitis for Acceleration	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	Nov 25, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging
Compact Vitis for Acceleration \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	May 04, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging
Compact Vitis for Acceleration \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Aug 17, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging
Compact Vitis for Acceleration \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 25, 2026	Info Vitis Embedded Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Linux PetaLinux Kernel Boot Bootflow elf c/c++ Debugging
Compact Edge AI Application Design Flow	WO (Workshop)	Development Tools & Methodology	Freiburg	3 days	May 27, 2026	Info edge ai design flow vitis Vivado phyton AMD adaptive socs alveo cards deep neural networks zynq ultrascale+ mpsoc
Compact Edge AI Application Design Flow	WO (Workshop)	Development Tools & Methodology	Munich	3 days	Sep 14, 2026	Info edge ai design flow vitis Vivado phyton AMD adaptive socs alveo cards deep neural networks zynq ultrascale+ mpsoc
Compact Edge AI Application Design Flow	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Nov 25, 2026	Info edge ai design flow vitis Vivado phyton AMD adaptive socs alveo cards deep neural networks zynq ultrascale+ mpsoc
Compact Edge AI Application Design Flow \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	May 27, 2026	Info edge ai design flow vitis Vivado phyton AMD adaptive socs alveo cards deep neural networks zynq ultrascale+ mpsoc
Compact Edge AI Application Design Flow \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 14, 2026	Info edge ai design flow vitis Vivado phyton AMD adaptive socs alveo cards deep neural networks zynq ultrascale+ mpsoc
Compact Edge AI Application Design Flow \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 25, 2026	Info edge ai design flow vitis Vivado phyton AMD adaptive socs alveo cards deep neural networks zynq ultrascale+ mpsoc
Compact Vitis AI	WO (Workshop)	Development Tools & Methodology	Freiburg	3 days	Jun 01, 2026	Info Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software
Compact Vitis AI	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Sep 01, 2026	Info Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software
Compact Vitis AI	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	Nov 10, 2026	Info Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software
Compact Vitis AI \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Jun 01, 2026	Info Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software
Compact Vitis AI \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Sep 01, 2026	Info Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software
Compact Vitis AI \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Nov 10, 2026	Info Vitis AI AI Software Tool Flow Blockdiagram SoC MPSoC Versal ACAP C C++ BSP Driver Board Support Package Profile Profiling Debugger System Debugger GCC GNU Eclipse Library Kernel c/c++ machine learning ML inference on the edge neuronal networks CNN Deep Learning Processing Unit DPU quantization embedded software
Compact FPGA Circuit Design Technique	WO (Workshop)	Development Tools & Methodology	Frankfurt / Main	3 days	May 11, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Compact FPGA Circuit Design Technique	WO (Workshop)	Development Tools & Methodology	Stuttgart	3 days	Aug 12, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Compact FPGA Circuit Design Technique	WO (Workshop)	Development Tools & Methodology	Berlin	3 days	Oct 21, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Compact FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	May 11, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Compact FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Aug 12, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
Compact FPGA Circuit Design Technique \| Online	OL (Online Live)	Development Tools & Methodology	Online	3 days	Oct 21, 2026	Info FPGA Clock Domain Crossing Flip Flop Architecture LUT BRAM Ressources CDC XDC reset Takt clock FPGA Architektur Schaltungsentwurf Schaltung architecture clocking synchronizer circuits IO Ultrascale Ultrascale+
FPGA Timing Constraints: A Comprehensive Overview	WE (Webinar)	Development Tools & Methodology	Online	1 hour	on demand	Info FPGA timing constraints AMD Vivado AMD FPGA design flow virtual clocks webinar
Think Before You Save! - Vivado Design Flow	WE (Webinar)	Development Tools & Methodology	Online	1 hour	on request	Info Vivado Implementation, Constraining, Vivado Design run, Hardware design flow, UltraFast UFD Ultrafast Design Methodology
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Training Formats

In-House

Individual and modular course content
Exclusive format focused on team-specific challenges
Length and pace adapted to your schedule
On-site training at the location of your choice

EXPLORE

Online Live

Online course
In-depth exercises in real-time
Remote access on utilized software and hardware

EXPLORE

Webinar

Good overview of a topic
Technical focus
Online

EXPLORE

Seminar

1-day technical deep dive
Free of charge
For developers, department heads, and managers

EXPLORE

Easy Start

Perfect for beginners and project managers
With a focus on practical exercises

EXPLORE

Workshop

Compact 1- to 3-day workshop
Ideal for developers
Theory and practice

EXPLORE

Power Workshop

5-day workshop
Very extensive further training
Practice-oriented on PC and evaluation board
Detailed treatment of technical topics

EXPLORE

Long Term Education

3 months training
For engineers and technicians
Including comprehensive training material

EXPLORE

More PLC2 Training
Categories

AMD Architecture

In today’s competitive world of electronic engineering the difference is made at the system architectural level. Making the right choices at the start of your design makes the difference between mediocre versus excellent results.

Learn more

Programming Languages

Familiarize yourself with the latest design methods to get the most out of your chosen technology. Learn the fundamentals and become an expert in HDL languages such as VHDL or SystemVerilog.

Learn more

Embedded Development

Are you a beginner in the embedded world or a very experienced embedded developer, we at PLC2 tailor our embedded classes to your level. Our workshops include everything you need to know on how to develop embedded solutions with AMD's wide range of SoCs.

Learn more

DSP & Image Processing

With their inherent flexibility, AMD FPGAs and SoCs are ideal for high-performance or multi-channel digital signal processing (DSP) applications that can take advantage of hardware parallelism.

Learn more

FPGA Connectivity & Protocols

How do you keep up with the edge network emerging applications that are redefining hardware requirements for electronic designers? Are you designing the next generation AI for IoT, embedded vision, hardware security, 5G communication or industrial/automotive automation for your company?

Learn more

How can we help?

Contact

Call PLC2

+49 7664 91313-15

Send an e-mail

michael.schwarz@plc2.de

FAQ

01. In which countries is PLC2 an Authorized Training Provider (ATP) of AMD?

PLC2 is an ATP in Cyprus, Czech Republic, Germany, Greece, Hungary, Poland, Slovakia, Slovenia, Switzerland, and Turkey.

02. What does AMD ATP stand for?

AMD Authorized Training Providers (ATPs) are expert instructors specializing in all aspects of FPGA and embedded design from software to systems and beyond. Courses offered leverage training materials specifically developed by AMD engineers and enhanced further via the specialized knowledge and expertise of AMD ATP instructors.

03. Can the training content be customized to specific FPGA and embedded design project requirements?

Yes. On request, we create customized training courses that are precisely tailored to your company’s tools, processes, and methods. See also our In-House training format.

04. Are there hands-on exercises in PLC2 training courses?

Depending on the course format, hands-on exercises are included in most of the training sessions, especially in workshops, power workshops, and online live courses.

05. How can I register for a PLC2 training course?

Go to the page of your desired training course and click the button »Book workshop«. You will jump directly to the booking form. Fill out the form and click submit. You will receive a confirmation e-mail immediately.

06. Can you help me with booking a room for the duration of my PLC2 training?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

07. What times in the day do PLC2 training courses start and end?

Our face-to-face and online courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours.

08. Are course materials provided in a PLC2 training?

All participants of paid courses will receive English training materials in electronic or paper form.

09. Will I receive a certificate upon completion of the PLC2 training course?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

10. Can I pay PLC2 training with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

11. What are the options for payment for PLC2 training?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

12. What is the deadline for payment for PLC2 training?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

13. What are the options for cancelling a PLC2 training?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

14. When will I receive a firm commitment as to whether the PLC2 training course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

15. What is the minimum number of participants for a PLC2 training?

We generally offer courses for 5 or more people. This means that if you would like to book a course at your location, either five people must register or you must pay for five participants, even if fewer people attend.

16. Can I book a PLC2 training course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

17. What language is the PLC2 training course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.

18. What formats are available in the Tools & Methodology category?

All PLC2 trainings are available in multiple formats (e.g. F2F, online or in-house) to fit different learning preferences and project constraints.

19. Do I need prior knowledge to participate in a PLC2 training course in the Tools & Methodology category?

Basic knowledge of digital logic and hardware description languages (VHDL / Verilog) is recommended but not mandatory. Many training courses show how to combine tools and methodologies in a targeted manner.

20. What general methods are taught in the Tools & Methodology training courses?

The training courses teach established engineering methodologies such as:
• Defining proper timing constraints
• FPGA design techniques
• Vitis HLS
• Test-driven development (TDD) for HDL
• Coverage-oriented verification
• Automated regression testing
• Workflow standardization (GitFlow, branching models)
• CI/CD best practices

21. Which specific tools are covered in the PLC2 Tools & Methodology training courses?

Depending on the course, we cover common tools and methodologies, including:
• FPGA design techniques, timing constraints
• EDA toolchains (e.g., Vivado, Vitis, Vitis HLS)
• Version control (Git, GitLab, GitHub)
• CI/CD systems (GitLab CI)
• Debugging and analysis tools
• Simulation and verification environments (OSVVM)
and other high-quality workflows for improving development quality.

22. What is covered in PLC2's Tools & Methodology training category?

Our Tools & Methodology training category focuses on the professional use of development, verification, and automation tools combined with proven engineering methodologies. The courses address how to structure FPGA and SoC projects efficiently, how to use tools correctly and reproducibly, and how to integrate best practices such as version control, CI/CD, verification frameworks, and timing-closure workflows into real-world projects. In addition, FPGA design techniques is an important topic which provides the technique to design reliable FPGA designs.

Development Tools & Methodology

Upcoming Trainings

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Tools & Methodology