Programming Languages

PLC2 is an ATP in Cyprus, Czech Republic, Germany, Greece, Hungary, Poland, Slovakia, Slovenia, Switzerland, and Turkey.

AMD Authorized Training Providers (ATPs) are expert instructors specializing in all aspects of FPGA and embedded design from software to systems and beyond. Courses offered leverage training materials specifically developed by AMD engineers and enhanced further via the specialized knowledge and expertise of AMD ATP instructors.

Yes. On request, we create customized training courses that are precisely tailored to your company’s tools, processes, and methods. See also our In-House training format.

Depending on the course format, hands-on exercises are included in most of the training sessions, especially in workshops, power workshops, and online live courses.

Go to the page of your desired training course and click the button »Book workshop«. You will jump directly to the booking form. Fill out the form and click submit. You will receive a confirmation e-mail immediately.

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

Our face-to-face and online courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours.

All participants of paid courses will receive English training materials in electronic or paper form.

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

We generally offer courses for 5 or more people. This means that if you would like to book a course at your location, either five people must register or you must pay for five participants, even if fewer people attend.

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.

Basic familiarity with digital logic concepts is recommended. For beginners, introductory trainings start with language fundamentals. Intermediate and advanced trainings assume understanding of combinational / sequential logic and basic HDL constructs to focus on deeper language usage and verification strategies.

Yes, trainings include verification-centric approaches using language extensions and methodologies such as OSVVM (Open Source VHDL Verification Methodology). These cover verification components, self-checking testbenches, functional coverage, and reusable libraries for robust testing.

Yes, SystemVerilog trainings focus on both design and verification aspects, including RTL constructs, interfaces, assertions (SVA), coverage, and verification methodologies.

A VHDL training covers foundational language concepts (types, operators, concurrency), synthesizable coding styles, state machine design, testbench development, and advanced topics like generics, packages, and parameterized architectures — all with practical examples suitable for real hardware projects.

These trainings are ideal for FPGA / ASIC designers, verification engineers, systems architects, and developers who want to deepen their understanding of hardware description languages and write robust, maintainable, and efficient code.

This training category focuses on hardware-oriented languages used for digital design and verification, including VHDL, Verilog / SystemVerilog, and domain-specific extensions and methodologies such as OSVVM for verification. The courses span from basic syntax and constructs to advanced coding techniques and industry best practices.