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FPGA Connectivity & Protocols

How do you keep up with the edge network emerging applications that are redefining hardware requirements for electronic designers? Are you designing the next generation AI for IoT, embedded vision, hardware security, 5G communication or industrial / automotive automation for your company? Then PLC2 can teach you how the state-of-art AMD products can be used in your application for processing and bridging needs including high bandwidth sensor and display interfaces, video processing and machine learning inferencing.

Upcoming Trainings

CourseFormatCategoryLocationDurationDate

Compact Versal Adaptive SoC: PCI Express Systems

WO (Workshop)

FPGA Connectivity & Protocols

Berlin

2 days

Jun 22, 2026

Info

Versal PCI Express Integrated Block for PCI Express Gen4 PL PCIe CPM PCIe High-Speed Interfaces Transceiver DDR4 PCB Design PCB Simulation ACAP PCIe endpoint root port DMA VCK190

Compact Versal Adaptive SoC: PCI Express Systems

WO (Workshop)

FPGA Connectivity & Protocols

Stuttgart

2 days

Oct 12, 2026

Info

Versal PCI Express Integrated Block for PCI Express Gen4 PL PCIe CPM PCIe High-Speed Interfaces Transceiver DDR4 PCB Design PCB Simulation ACAP PCIe endpoint root port DMA VCK190

Designing with Ethernet MAC Controllers

WO (Workshop)

FPGA Connectivity & Protocols

Stuttgart

2 days

May 28, 2026

Info

Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP

Designing with Ethernet MAC Controllers

WO (Workshop)

FPGA Connectivity & Protocols

Freiburg

2 days

Sep 03, 2026

Info

Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP

Designing with Ethernet MAC Controllers

WO (Workshop)

FPGA Connectivity & Protocols

Munich

2 days

Nov 05, 2026

Info

Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP

Designing with Ethernet MAC Controllers | Online

OL (Online Live)

FPGA Connectivity & Protocols

Online

2 days

May 28, 2026

Info

Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP

Designing with Ethernet MAC Controllers | Online

OL (Online Live)

FPGA Connectivity & Protocols

Online

2 days

Sep 03, 2026

Info

Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP

Designing with Ethernet MAC Controllers | Online

OL (Online Live)

FPGA Connectivity & Protocols

Online

2 days

Nov 05, 2026

Info

Connectivity Ethernet udp tcp layer high-speed highspeed protocol Phy GMII SGMII MAC UDP TCP/IP

Compact Zynq UltraScale+ RFSoC

WO (Workshop)

FPGA Connectivity & Protocols

Freiburg

3 days

May 18, 2026

Info

RFSoC ADC DAC RF UltraScale+ Data Converter

Compact Zynq UltraScale+ RFSoC

WO (Workshop)

FPGA Connectivity & Protocols

Frankfurt / Main

3 days

Sep 28, 2026

Info

RFSoC ADC DAC RF UltraScale+ Data Converter

Compact Zynq UltraScale+ RFSoC

WO (Workshop)

FPGA Connectivity & Protocols

Munich

3 days

Dec 07, 2026

Info

RFSoC ADC DAC RF UltraScale+ Data Converter

Compact Versal Adaptive SoC: Power and Board Design

WO (Workshop)

FPGA Connectivity & Protocols

3 days

all year on request

Info

Embedded ACAP board design integrity power Versal Cortex-A72 Cortex-R5 NoC DDR4 AXI XPE power design Power Supply PDM Signal Integrity Reflection Crosstalk IBIS

Compact Versal Adaptive SoC: Power and Board Design | Online

OL (Online Live)

FPGA Connectivity & Protocols

Online

3 days

all year on request

Info

Embedded ACAP board design integrity power Versal Cortex-A72 Cortex-R5 NoC DDR4 AXI XPE power design Power Supply PDM Signal Integrity Reflection Crosstalk IBIS

Compact UltraScale: Serial Transceivers

WO (Workshop)

FPGA Connectivity & Protocols

Berlin

3 days

Jun 24, 2026

Info

UltraScale Serial Transceiver GTX GTH GTY 8B/10B 64B/66B 64B/67B UltraScale+ gearbox PLL KCU105

Compact UltraScale: Serial Transceivers

WO (Workshop)

FPGA Connectivity & Protocols

Frankfurt / Main

3 days

Sep 14, 2026

Info

UltraScale Serial Transceiver GTX GTH GTY 8B/10B 64B/66B 64B/67B UltraScale+ gearbox PLL KCU105

Compact UltraScale: Serial Transceivers | Online

OL (Online Live)

FPGA Connectivity & Protocols

Online

3 days

Jun 24, 2026

Info

UltraScale Serial Transceiver GTX GTH GTY 8B/10B 64B/66B 64B/67B UltraScale+ gearbox PLL KCU105

Compact UltraScale: Serial Transceivers | Online

OL (Online Live)

FPGA Connectivity & Protocols

Online

3 days

Sep 14, 2026

Info

UltraScale Serial Transceiver GTX GTH GTY 8B/10B 64B/66B 64B/67B UltraScale+ gearbox PLL KCU105

Compact UltraScale: High-Speed Memory Interfacing

WO (Workshop)

FPGA Connectivity & Protocols

3 days

all year on request

Info

7Series DDR3 memory Memory Controller PCB Design PCB Design Rules Debugging DDR3 UltraScale UltraScale+ DDR4 memory

Compact UltraScale: High-Speed Memory Interfacing | Online

OL (Online Live)

FPGA Connectivity & Protocols

Online

3 days

all year on request

Info

7Series DDR3 memory Memory Controller PCB Design PCB Design Rules Debugging DDR3 UltraScale UltraScale+ DDR4 memory

Compact UltraScale: Board Design and Signal Integrity

WO (Workshop)

FPGA Connectivity & Protocols

3 days

all year on request

Info

UltraScale Power Supply board design power integrity Signal Integrity Reflection Crosstalk HyperLynx IBIS AMI Models PCB Simulation High-Speed Interfaces Transceiver PCI Express DDR4 PCB Design UltraScale+ board design power design Power Supply XPE Signal Integrity Reflection Crosstalk IBIS

Compact UltraScale: Board Design and Signal Integrity | Online

OL (Online Live)

FPGA Connectivity & Protocols

Online

3 days

all year on request

Info

UltraScale Power Supply board design power integrity Signal Integrity Reflection Crosstalk HyperLynx IBIS AMI Models PCB Simulation High-Speed Interfaces Transceiver PCI Express DDR4 PCB Design UltraScale+ board design power design Power Supply XPE Signal Integrity Reflection Crosstalk IBIS

AXI Interface Technology

WO (Workshop)

FPGA Connectivity & Protocols

Frankfurt / Main

2 days

Jun 18, 2026

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

WO (Workshop)

FPGA Connectivity & Protocols

Berlin

2 days

Sep 10, 2026

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology

WO (Workshop)

FPGA Connectivity & Protocols

Munich

2 days

Nov 02, 2026

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology | Online

OL (Online Live)

FPGA Connectivity & Protocols

Online

2 days

Jun 18, 2026

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology | Online

OL (Online Live)

FPGA Connectivity & Protocols

Online

2 days

Sep 10, 2026

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

AXI Interface Technology | Online

OL (Online Live)

FPGA Connectivity & Protocols

Online

2 days

Nov 02, 2026

Info

FPGA AXI Interface Protocoll Protocol AMBA stream streaming lite full valid ready channels interconnect latency interface bus connectivity optimization sharing DDRAM performance

Compact UltraScale: Integrated PCI Express Systems

WO (Workshop)

FPGA Connectivity & Protocols

Freiburg

3 days

May 04, 2026

Info

UltraScale PCI Express Integrated Block for PCI Express Gen3 PL PCIe UltraScale+ PCIe endpoint root port DMA KCU105

Compact UltraScale: Integrated PCI Express Systems

WO (Workshop)

FPGA Connectivity & Protocols

Munich

3 days

Sep 01, 2026

Info

UltraScale PCI Express Integrated Block for PCI Express Gen3 PL PCIe UltraScale+ PCIe endpoint root port DMA KCU105

Compact UltraScale: Integrated PCI Express Systems

WO (Workshop)

FPGA Connectivity & Protocols

Berlin

3 days

Dec 01, 2026

Info

UltraScale PCI Express Integrated Block for PCI Express Gen3 PL PCIe UltraScale+ PCIe endpoint root port DMA KCU105

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FAQ

01. In which countries is PLC2 an Authorized Training Provider (ATP) of AMD?

PLC2 is an ATP in Cyprus, Czech Republic, Germany, Greece, Hungary, Poland, Slovakia, Slovenia, Switzerland, and Turkey.

02. What does AMD ATP stand for?

AMD Authorized Training Providers (ATPs) are expert instructors specializing in all aspects of FPGA and embedded design from software to systems and beyond. Courses offered leverage training materials specifically developed by AMD engineers and enhanced further via the specialized knowledge and expertise of AMD ATP instructors.

03. Can the training content be customized to specific FPGA and embedded design project requirements?

Yes. On request, we create customized training courses that are precisely tailored to your company’s tools, processes, and methods. See also our In-House training format.

04. Are there hands-on exercises in PLC2 training courses?

Depending on the course format, hands-on exercises are included in most of the training sessions, especially in workshops, power workshops, and online live courses.

05. How can I register for a PLC2 training course?

Go to the page of your desired training course and click the button »Book workshop«. You will jump directly to the booking form. Fill out the form and click submit. You will receive a confirmation e-mail immediately.

06. Can you help me with booking a room for the duration of my PLC2 training?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

07. What times in the day do PLC2 training courses start and end?

Our face-to-face and online courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours.

08. Are course materials provided in a PLC2 training?

All participants of paid courses will receive English training materials in electronic or paper form.

09. Will I receive a certificate upon completion of the PLC2 training course?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

10. Can I pay PLC2 training with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

11. What are the options for payment for PLC2 training?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

12. What is the deadline for payment for PLC2 training?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

13. What are the options for cancelling a PLC2 training?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

14. When will I receive a firm commitment as to whether the PLC2 training course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

15. What is the minimum number of participants for a PLC2 training?

We generally offer courses for 5 or more people. This means that if you would like to book a course at your location, either five people must register or you must pay for five participants, even if fewer people attend.

16. Can I book a PLC2 training course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

17. What language is the PLC2 training course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.

18. What formats are available in the training category Connectivity & Protocols?

All PLC2 trainings are available in multiple formats (e.g. F2F, online or in-house) to fit different learning preferences and project constraints.

19. What prerequisites do I need for a training in the category Connectivity & Protocols?

Participants should have a basic understanding of digital logic. Prior experience with microcontrollers, FPGA / SoC platforms, or firmware development improves learning outcomes.

20. What hardware platforms are supported in Connectivity & Protocols training?

Trainings use representative embedded, FPGA / SoC platforms. Specific platforms may vary by course, but real hardware examples, reference designs, and development kits are used wherever possible to illustrate interfaces in action.

21. Does the training in the category Connectivity & Protocols cover protocol implementation or just theory?

Courses combine protocol theory with practical implementation, integration, hands-on excercises, compliance considerations, and real-world debugging techniques. Participants learn how protocols work and how to implement and validate them in hardware and firmware contexts.

22. What types of communication protocols are included in a training of the category Connectivity & Protocols?

Connectivity trainings cover a mix of low-speed serial interfaces (I²C, SPI, UART) and high-speed interfaces (PCIe, USB, Ethernet, Aurora, DDR)
Coverage varies by course, with practical configuration, implementation, and protocol-specific considerations.

23. Who is training in the category Connectivity & Protocols designed for?

These trainings are ideal for embedded and FPGA / SoC engineers, system architects, firmware developers, hardware designers, and integration engineers who need to design, implement, debug, or optimize communication interfaces within embedded systems, industrial automation, or networked applications.

24. What topics are covered in the training category Connectivity & Protocols?

Connectivity focuses on protocols, interfaces, and technologies used to enable communication between embedded systems, FPGAs, SoCs, sensors, and networks. This includes serial interfaces (e.g., I²C, SPI, UART), high-speed buses (e.g., PCIe, Ethernet), industrial fieldbuses (e.g., CAN, EtherCAT, PROFINET), wireless protocols, and system-level integration best practices for robust and high-performance data exchange.