Versal Adaptive SoC for the System Architect | Online
With Versal™ adaptive SoC, AMD offers a highly integrated technology, the adaptive compute acceleration platform. The devices of this family exhibit a heterogeneous architecture of compute engines on a common programmable infrastructure. This workshop describes the adaptive SoC architecture to foster insight into the optimal assignment of the available building blocks for demanding tasks.
Versal™ offers a high-performant multiprocessor Arm® cluster as evolved from the Zynq™ technologies and adds further hardened IPs beyond the well established Programmable Logic (PL) to further support designs with various computation requirements. The range of IPs allows on device High Bandwidth Memory (HBM) to the highest speed transceiver up to 112 Gbps, depending on the particular choice of a respective subfamily. For compute intense challenges, specific IPs (AI Engines) are available, to accelerate tasks deploying large vectorization gains. All compute engines are supported by a device-wide Network on Chip (NoC) to guarantee bandwidth within the device, to expose memory controllers and help with timing closure in the design. The programmability of this infrastructure constitutes a flexible hardware platform.
This platform concept is further supported by a full stack of software and hardware functions to allow focus on application development. For best results, the partitioning of an application needs to be derived along tasks that can benefit from the respective Versal™ features. This approach to designing with these devices is shown from platform generation to integration, adding simulation and debugging insights. The workshop is particularly suitable for system engineers and developers in the planning phase of complex applications.
Due to accompanying exercises, the course offers in-depth and practice-oriented training. Attendees of the online live training will perform the practical exercises in real time with instructor assistance.
Course language: English

Contact
Michael Schwarz l Head of Training
+49 7664 91313-15
Details
Applicable technologies
AMD Versal™ adaptive SoCRequirements
Basic knowledge in processor system architecture and AMD FPGA architectureBasic knowledge of the programming language C/C++
Duration
2 daysFee (net per person)
€ 1,500Inclusive
Training materialAgenda
01
Introduction to Versal™ adaptive SoC
02
Versal™ architecture overview
03
Versal™ adaptable engines (PL)
04
IO connectivity and timer resources
05
Processing system
06
PMC, boot and configuration
07
System interrupts
08
Intelligent engines
09
NoC introduction and device memory
10
Serial transceivers
11
Introduction to PCIe®, CPM, and CCIX
12
Security features
13
System and solution planning – application partitioning
14
Hardware, IP, and platform development methodology
15
System integration and validation methodology
16
Exercises
01. Design tool flow
02. Application development
03. NoC introduction
04. System Level Simulation
05. Versal™ adaptive SoC platform creation
Dates
Versal Adaptive SoC for the System Architect | Online
OL
Online
Apr 16, 2026
Versal Adaptive SoC for the System Architect | Online
OL
Online
Aug 13, 2026
Versal Adaptive SoC for the System Architect | Online
OL
Online
Nov 16, 2026
Available formats for this training
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FAQ
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PLC2 is an ATP in Cyprus, Czech Republic, Germany, Greece, Hungary, Poland, Slovakia, Slovenia, Switzerland, and Turkey.
02. What does AMD ATP stand for?
AMD Authorized Training Providers (ATPs) are expert instructors specializing in all aspects of FPGA and embedded design from software to systems and beyond. Courses offered leverage training materials specifically developed by AMD engineers and enhanced further via the specialized knowledge and expertise of AMD ATP instructors.
03. Can the training content be customized to specific FPGA and embedded design project requirements?
Yes. On request, we create customized training courses that are precisely tailored to your company’s tools, processes, and methods. See also our In-House training format.
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