Compact VHDL for Simulation
Programmable logic devices like FPGAs have been established in daily life. They can be found in mobile phones, IoT devices, cars, or cloud data centers. Their area of operation is as broad as their size. FPGAs are used as, but are not limited to: protocol adapters, signal converters, or accelerators for video, radar, and sensor data processing. The design of digital circuits on this scale needs a powerful hardware description language which offers different levels of abstraction, so an engineer can create a digital hardware design in a quick and effective way. VHDL fulfills these requirements.
VHDL is a strongly typed hardware description language that prohibits typical programming mistakes in the coding phase. Usually, VHDL is used on the Register Transfer Level (RTL) to design digital circuits of any complexity. Apart from the language constructs for synthesis, VHDL offers a wide range of functionality to describe complex verification models. Thus, it is possible to verify digital designs from simple gate-up to complicated System on Chip (SoC) before going to lab tests. With recourse to already well-known VHDL language features, this workshop will deepen the knowledge in VHDL and enable the attendee to create simulations with the VHDL test bench concept. The taught language constructs are based on the IEEE Std. 1076-2008 language revision.
Basic knowledge of the hardware description language VHDL, e.g. from »Compact VHDL for Synthesis« is desirable.
Due to accompanying exercises, the course offers in-depth and practice-oriented training. Attendees of the online live training will perform the practical exercises in real time with instructor assistance.
Course language: German (English possible on request)
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Contact
Michael Schwarz l Head of Training
+49 7664 91313-15
Details
Applicable technologies
FPGA technologiesRequirements
Basic knowledge of the hardware description language VHDLDuration
2 daysFee (net per person)
€ 1,900Inclusive
Training materialPlus beverages during breaks
Lunch
Agenda
01
VHDL recap
Process and concurrency
Wait statements, delta cycles
Types, operators, attributes
Control structures
Functions/procedures
Generics
02
Testbench concept
Inline testbenches
Modulare testbenches
Code vs. functional coverage
Assertions
03
Test planning
Directed testing
Random testing
04
Stimuli and checks
Simple stimuli generation
Analogue stimuli
Random stimuli
Timing checks
Self-checking testbench
05
File I/O
Reading and writing files
Logging
06
Modelling of external components
Example case: UART
Dates
Compact VHDL for Simulation
WO
Frankfurt / Main
Jun 18, 2026
Compact VHDL for Simulation
WO
Stuttgart
Sep 24, 2026
Compact VHDL for Simulation
WO
Munich
Nov 26, 2026
Available formats for this training
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PLC2 is an ATP in Cyprus, Czech Republic, Germany, Greece, Hungary, Poland, Slovakia, Slovenia, Switzerland, and Turkey.
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AMD Authorized Training Providers (ATPs) are expert instructors specializing in all aspects of FPGA and embedded design from software to systems and beyond. Courses offered leverage training materials specifically developed by AMD engineers and enhanced further via the specialized knowledge and expertise of AMD ATP instructors.
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