Compact SystemVerilog for Synthesis

Workshop

The continuously rising demand for highly complex programmable logic in combination with ever-increasing clock rates hold challenges for the users. SystemVerilog (IEEE 1800) as the successor of the already very popular Verilog Hardware Description Language (HDL) brings all features to describe logic in a scalable and reusable fashion, extending the design methods seamlessly into verification. It has become a major tool of choice in FGPA and ASIC designs, supported by virtually all EDA vendor tools.

In this workshop, SystemVerilog is presented using a set of modern and powerful HDL-based design techniques that support a high design quality for any physical target. The examples and labs during the sessions aim at FPGA fabric as a demonstration vehicle for language features, while SystemVerilog is even more established in ASIC designs. The course presents the SystemVerilog concepts and core syntax and fosters insight into its successful usage. Also, attendees are introduced to basic modular design elements as well as principal verification approaches set within the hardware programming language.

All theoretical topics are complemented with PC-based exercises in synthesis and simulation. Within these exercises, the attendees will create multiple SystemVerilog modules that constitute a larger design context. The development cycle will be closed by implementing and - for the face-to-face attendees - porting such a design onto an FPGA evaluation board, allowing you to gain insight into device configuration and observability of an operational design.

The extended SystemVerilog features for verification are not covered in this agenda. To gain insight into these language features, please review the workshop »SystemVerilog Advanced Verification for FPGA Design« or consult PLC2 Training.

Course language: German (English possible on request)

Book workshop

Contact

Michael Schwarz l Head of Training

+49 7664 91313-15

michael.schwarz@plc2.de

Details

Applicable technologies

Generic, AMD FPGAs and adaptive SoCs

Requirements

Basic knowledge of digital technology

Duration

3 days

Fee (net per person)

€ 2,500

Inclusive

Training material
Plus beverages during breaks
Lunch

Agenda

Introduction

SystemVerilog concepts

Keywords

Data types

Net and variable data types

Aggregate types

Arrays and strings
User defined types and type casting

Operators

Data flow modeling

Continuous assignments
Blocking assignments

Procedural statements

Control flow statements

Functions and tasks

Hierarchy constructs

Module and packages
Generate statements
Interfaces

Introduction to FSM design

Testbenches

File I/O

Application Programming Interfaces (API)

DPI, PLI/VPI

Targeting AMD FPGAs

Dates

Compact SystemVerilog for Synthesis

Frankfurt / Main

Apr 27, 2026

Book now

Compact SystemVerilog for Synthesis

Freiburg

Jul 27, 2026

Book now

Compact SystemVerilog for Synthesis

Munich

Oct 26, 2026

Book now

Available formats for this training

Compact SystemVerilog for Synthesis

3 days

€ 2,500

Workshop

Compact SystemVerilog for Synthesis | Online

3 days

€ 2,100

Online Live

This might also interest you...

Course	Format	Category	Location	Duration	Date
SystemVerilog Advanced Verification for FPGA Design \| Online	OL (Online Live)	Programming Languages	Online	3 days	all year on request	Info FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis
SystemVerilog Advanced Verification for FPGA Design	WO (Workshop)	Programming Languages		3 days	all year on request	Info FPGA HDL SystemVerilog Assertions Language Verification Hardware FPGA Programmable Logic Simulation Coverage Synthese Synthesis
Professional VHDL \| Online	OL (Online Live)	Programming Languages	Online	5 days	May 18, 2026	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL \| Online	OL (Online Live)	Programming Languages	Online	5 days	Jul 20, 2026	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL \| Online	OL (Online Live)	Programming Languages	Online	5 days	Oct 12, 2026	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL \| Online	OL (Online Live)	Programming Languages	Online	5 days	Dec 07, 2026	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	PW (Power Workshop)	Programming Languages	Freiburg	5 days	May 18, 2026	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	PW (Power Workshop)	Programming Languages	Freiburg	5 days	Jul 20, 2026	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	PW (Power Workshop)	Programming Languages	Stuttgart	5 days	Oct 12, 2026	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional VHDL	PW (Power Workshop)	Programming Languages	Freiburg	5 days	Dec 07, 2026	Info FPGA HDL VHDL Synthesis Language Verification Hardware FPGA Programmable Logic Simulation Implementierung Synthese Bitstream bit Vivado Vitis
Professional FPGA \| Online	OL (Online Live)	AMD Architecture	Online	5 days	May 18, 2026	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA \| Online	OL (Online Live)	AMD Architecture	Online	5 days	Jul 13, 2026	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA \| Online	OL (Online Live)	AMD Architecture	Online	5 days	Oct 26, 2026	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA	PW (Power Workshop)	AMD Architecture	Freiburg	5 days	May 18, 2026	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA	PW (Power Workshop)	AMD Architecture	Frankfurt / Main	5 days	Jul 13, 2026	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Professional FPGA	PW (Power Workshop)	AMD Architecture	Freiburg	5 days	Oct 26, 2026	Info FPGA Architecture Architektur LUT BRAM Ressources reset Takt clock Flip Flop IP Core clocking resources coding techniques DSP timing constraints IO XDC
Items per page 10 25 50 100 prev next showing: 1 to 2 (2)

How can we help?

Contact

Call PLC2

+49 7664 91313-15

Send an e-mail

michael.schwarz@plc2.de

FAQ

01. In which countries is PLC2 an Authorized Training Provider (ATP) of AMD?

PLC2 is an ATP in Cyprus, Czech Republic, Germany, Greece, Hungary, Poland, Slovakia, Slovenia, Switzerland, and Turkey.

02. What does AMD ATP stand for?

AMD Authorized Training Providers (ATPs) are expert instructors specializing in all aspects of FPGA and embedded design from software to systems and beyond. Courses offered leverage training materials specifically developed by AMD engineers and enhanced further via the specialized knowledge and expertise of AMD ATP instructors.

03. Can the training content be customized to specific FPGA and embedded design project requirements?

Yes. On request, we create customized training courses that are precisely tailored to your company’s tools, processes, and methods. See also our In-House training format.

04. Are there hands-on exercises in PLC2 training courses?

Depending on the course format, hands-on exercises are included in most of the training sessions, especially in workshops, power workshops, and online live courses.

05. How can I register for a PLC2 training course?

Go to the page of your desired training course and click the button »Book workshop«. You will jump directly to the booking form. Fill out the form and click submit. You will receive a confirmation e-mail immediately.

06. Can you help me with booking a room for the duration of my PLC2 training?

If you need a room for a face-to-face course, please contact us. We will support you in choosing suitable accommodation.

07. What times in the day do PLC2 training courses start and end?

Our face-to-face and online courses start daily at 9 a.m. (CET/CEST) and end at 5 p.m., with two coffee breaks and an extended lunch break. The total course time per day is 6 hours.

08. Are course materials provided in a PLC2 training?

All participants of paid courses will receive English training materials in electronic or paper form.

09. Will I receive a certificate upon completion of the PLC2 training course?

Each participant of a paid PLC2 course will receive a signed certificate of attendance at the end of the course.

10. Can I pay PLC2 training with Training Credits (TCs)?

Of course, you can also pay for your training using your available TCs (Training Credits). We will then invoice AMD directly. If you do not have sufficient credit for the booked training, the difference can be paid for with an additional payment. The additional charge will be invoiced directly to you.

11. What are the options for payment for PLC2 training?

You can pay us via bank transfer or with TCs (Training Credits). Unfortunately, payment via debit, credit card, or PayPal is not possible.

12. What is the deadline for payment for PLC2 training?

Payment is due 14 days after the invoice date, without deduction. Please transfer the amount within that time.

13. What are the options for cancelling a PLC2 training?

You can cancel free of charge up to 14 days before the course starts. If you have to cancel at short notice due to illness or other reasons, you have the option of adding a substitute participant or of making up the course at a later date (within 6 months).

14. When will I receive a firm commitment as to whether the PLC2 training course will take place?

You will receive binding confirmation 7 days before the course begins as to whether it will go ahead.

15. What is the minimum number of participants for a PLC2 training?

We generally offer courses for 5 or more people. This means that if you would like to book a course at your location, either five people must register or you must pay for five participants, even if fewer people attend.

16. Can I book a PLC2 training course that is given in English?

If you need a course that is officially advertised as given in German to be given in English, please contact us. We will try to make that possible for you.

17. What language is the PLC2 training course in?

Our webinars and online courses are conducted in English. All our F2F training courses are generally conducted in German. Feel free to contact us if you need face-to-face training in English or online training in German.