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VHDL Explained

Flexible HDL Designs

Generic Hardware Description Language (HDL) designs are the key to flexibility and success in projects. There are several aspects to flexibility:
 
1. Use generic (constant) parameters to tune a components behavior.
 
Examples are:

  • Baudrate (UART) or timing parameters (I²C timing).
  • Implementation details like LUT-RAM vs. BlockRAM vs. UltraRAM.
  • Enable debugging (instantiate ILA).
  • CRC polynomial.
  • Statemachine mode like device vs. host.
  • Resource consumption like FIFO depth.

2. Use unconstrained ports to implement a single component for variants of the same interface. An unconstrained record datatype can describe a whole AXI4Lite bus independent of the number of data bit, address bits, etc. Thus, a single AXI4Lite CDC component can server all bus combination and avoids copy-paste code. Compared a design using generics, it needs less parameters and adjusts itself in case a bus parameter is changed.

3. Use a modular design where every component as a single responsibility. If features are not mixed within basic components, components can be updated, replaced and reused all over the design. This allows systems architects to compose high-level features and more complex components (IP cores) based on basic elements.
 
As these basic elements are small, the can be tested comprehensively. This ensures confidence when reusing these components. In addition design time is reduced because tested code exists, but also because designs know how to integrate these components.

4. No magic numbers! Avoiding magic numbers eases code reviews and maintenance of complex designs. At easiest, configuration parameters are constants within architectures. At a more sophisticated level, some parameters get promoted to generics. If a specification contains a calculation involving multiple parameters are magic numbers, do not use your calculator, let the VHDL compiler calculate it for you. This allows for later reviews.

Did you know VHDL accepts 32-bit decimal literals?
 

constant DELAY_COUNTER_MAX : unsigned := 32d”51859″;

 
Now let me add a last item.

5. Be prepared for change! Either YOU, your boss or your customer will change one’s mind. There will be updated requirements. No design is ever completely preplanned and fixed. Based on my experience, you should plan for 2 changes: The first one should be easy to implement by using the flexibility in the design we discussed above. The second one, if needed, should be possible with moderate effort.

The upcoming webinar »The PoC-Library Part 4: Memory Implementations« on 02.12.2025 will continue on other aspects for flexibility. Register for free!