VHDL Explained
Understanding std_logic_vector Direction
What direction does a std_logic_vector have, if you assign a bit-string literal to an unconstrained port in VHDL? Let us assume you have this entity declaration:
entity myComponent is
port (
signal data : in std_logic_vector
);
and this instantiation:
my : entity work.myComponent
port map (
data => 32x”0815″
);
Is data in ascending order (‘to’) or descending order (‘downto’)?
To solve this question, we need to look at VHDL’s type definitions:
subtype std_logic_vector is (resolved) std_ulogic_vector;type
std_ulogic_vector is array (natural range <>) of
std_ulogic;subtype natural is integer range 0 to integer’high;
A std_logic_vector is a resolved subtype of std_ulogic_vector. A std_ulogic_vector is an array of std_ulogic elements. This array accepts natural indices. The natural is defined in ascending order using ‘to’.
Thus the value of our data port is x”00000815″ as std_logic_vector(0 to 31).
You can access the direction with attribute ‘ascending returning true or false.
As slicing arrays needs to be done in the direction its declaration, you can define an alias using ‘downto’ direction:
salias myData : std_logic_vector(31 downto 0) is data;
Got curious? There is much more to uncover about how VHDL really behaves.
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