Introduction to the AMD Vivado Logic Analyzer & Additional Debug IP Cores

Webinar

The Vivado Integrated Logic Analyzer (ILA) is fully integrated in the Vivado™ tool suite. This provides the possibility of FPGA internal logic analysis along with different configurations of the trigger unit and data storage options, to ideally fit the requirements of the measurement task. Even HDL novices may take advantage of this alternative verification mechanism. It may complement HDL simulations when bringing new systems into service.

In this webinar, we will talk about the Vivado Integrated Logic Analyzer but also about other verification IP cores like the VIO (Virtual Input/Output) and the IBERT (Integrated Bit Error Ratio Tester) IP core. While the Vivado Integrated Logic Analyzer is used to trigger and sample data, the VIO core can be used to monitor current values of different signals or even control signals in the FPGA by using the JTAG connection to the FPGA. The IBERT core is very useful when analyzing high speed connections, which are established by using the integrated transceivers of specific AMD FPGAs.

After talking about the topics described above, there will be a live demo, where the usage of the Vivado Integrated Logic Analyzer and the VIO core will be shown.

Course language: English

Book webinar

Contact

Michael Schwarz l Head of Training

+49 7664 91313-15

michael.schwarz@plc2.de

Details

Duration

11-12 am CEST

Dates

Available formats for this training

Introduction to the AMD Vivado Logic Analyzer & Additional Debug IP Cores

11-12 am CEST

€ 0

Webinar

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