VHDL Explained
From Closely Related Types to Subtypes -
VHDL 2008 Explained
Why can we assign values between std_logic_vector and std_ulogic_vector? And why couldn’t we in the past?
Since VHDL-2008, std_logic_vector is a subtype of std_ulogic_vector, thus values can be assigned between objects of these types without type conversion. Before VHDL-2008, both types were independent array types with similar structure and therefore so called closely related types. For such related types VHDL automatically defines a conversion function, so the users do not need to write a conversion function themselves, but the users need to apply it.
Code often looked like that:
my : entity myComponent
port map (
slv1 => std_logic_vector(sulv1), — in
std_ulogic_vector(slv2) => sulv2, — out
std_ulogic_vector(slv3) => std_logic_vector)sulv3) — inout
);
Let us have a look at VHDL’s type definitions for the std_logic family before VHDL-2008:
type std_ulogic is (
‘U’, — Uninitialized
‘X’, — Forcing Unknown
‘0’, — Forcing 0
‘1’, — Forcing 1
‘Z’, — High Impedance
‘W’, — Weak Unknown
‘L’, — Weak 0
‘H’, — Weak 1
‘-‘ — Don’t care
);
subtype std_logic is resolved std_ulogic; — apply resolution function to get a resolved subtype
type std_ulogic_vector is array (natural range <>) of std_ulogic;
type std_logic_vector is array (natural range <>) of std_logic;
Here we see, both types are array types. One has std_ulogic elements, the other has std_logic elements. Both types are no subtypes of each other (like integer and natural), thus type conversions are needed when assigning from one to the other. Fortunately, both types a similar structure:
(1) an array type using natural indices
(2) elements that are subtypes of each other
Thus, both array types are considered closely related types by the language and it defines type conversions.
Now let us look at VHDL-2008. The new type definition of std_logic_vector is as follows:
type std_ulogic_vector is array (natural range <>) of std_ulogic;
subtype std_logic is resolved std_ulogic;
subtype std_logic_vector is (resolved) std_ulogic_vector;
Here we see std_logic_vector is a subtype of std_ulogic_vector and similar to the definition of std_logic, a resolution function gets applied. The difference here is the parenthesis around the resolution function. This indicates to apply the resolution function per array element (individually).
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