Description
Modern test and validation systems, particularly in the automotive, industrial automation, aerospace, and defence sectors, generate ever-increasing volumes of data. High-resolution cameras, radar, LiDAR, and other sensor systems transmit their data streams via multi-gigabit Ethernet connections, quickly pushing conventional PC-based systems to their performance limits. The mere transmission of the data is often not the biggest challenge. Rather, protocol processing, packet management, timestamping, synchronization, and the continuous storage and playback of the data place a significant load on the CPU.
This reduces the computing power available for analysis, visualization, or control tasks and makes it difficult to process multiple parallel data sources. The typically high bandwidth in such application can be handled effectively by an MPSoC device.
Methodology
A scalable solution involves offloading the time-critical and data-intensive processing steps from the host CPU to a dedicated hardware platform. Multiple 10 Gbit/s lines are processed immediately upon receipt, with Ethernet protocols decoded, data streams synchronized, timestamps generated, and application-specific preprocessing steps already executed within the hardware.
The in the PL acquired data is written directly to the DDR memory by using a DMA. It is now possible to access that data either from the Arm Cortex-R5 cores, the Arm Cortex-A53 cores or both. Time critical functionalities should be handled by the R5 using an RTOS or bare metal code. Non-time-critical parts can be processed by an embedded Linux which is running on the A53 cores.
To further process or distribute the data in the PL, an additional DMA can be used to transfer the data back from the DDR memory. In the following block diagram, the complete path through the device is seen:
Figure 1: Data path through the MPSoC device
Conclusion
Hardware-based processing allows multiple data streams to be processed in parallel with constant latency. This architecture can be flexibly extended to include additional protocols, data filters, trigger mechanisms, or application-specific acceleration functions without requiring fundamental changes to the host system’s software architecture.
This architecture is particularly well-suited for applications involving continuous multi-gigabit data streams, where high data rates, low latencies, and deterministic processing are critical. Typical areas of application include robotics, sensor fusion, industrial image processing, automated test systems, network logging, high-speed measurement technology, and real-time data analysis in safety-critical systems.
