Open-Source VHDL
IP Core Library

As a comprehensive open-source library of synthesizable IP cores, designed for FPGA and ASIC development, the PoC-Library supports a wide range of FPGA devices from different vendors.

With its strong focus on flexibility, portability, performance, and usability, you are provided with a solid foundation for building reliable, scalable, and vendor-neutral designs.

Open-Source Know-How at PLC2:
From Training to Development

PLC2 has over eight years of experience working with open-source technologies, which we use in our training sessions and daily project work.

The key tool in this context is the Pile of Cores (PoC), an open-source framework whose goals align closely with PLC2’s design and architecture philosophy. By using the library in nearly all of our customer projects and PLC2 products, we have gained independence from vendor-specific IP cores.

GitHub Repository

Documentation

PLC2’s Contribution

Modifications

– Component name cleanups
– Port name and generic cleanups
– Bug fixes in existing moduls
– New generics for preexisting modules
– New modes for preexisting modules

AXI4

– Multiplexer and Demultiplexer
– FIFO and variants
– Clock Domain Crossing
– AXI4 to AXI4-Lite Adapter

AXI4-Lite

– Demultiplexer
– FIFO
– Clock Domain Crossing
– Generic Register
– UART
– OCRAM Adapter
– DRP Bridge
– High Resolution Clock

AXI4-Stream

– FIFO and variants
– Clock Domain Crossing
– Multiplexer / Demultiplexer
– Stage

PoC Release 3.0

With years of internal development on the PoC-Library to meet our own and our customers’ needs, the internal PoC-Library fork has been constantly grown and matured. Most additions focus on the AXI bus infrastructure to replace standard IP cores from the Vivado™ toolchain. This effort enabled PLC2 with higher flexibility, less resource consumption, and better development insights while debugging.

In collaboration with the public PoC-Library maintainers our contributions have been reviewed and accepted and the PoC-Library made a version increment from v2.3. to v3.0.

For this major release, PLC2 published a set of AXI4 and AXI4-Lite multiplexer and demultiplexer components, which enables users to build AXI4 interconnect structures. The release was accompanied by other new components like an OutOfOrderBuffer.

The PoC Library has reached over 200 IP cores and its test suite doubled in size to 54 testcases. More testcases will transition to OSVVM style tests within the next minor releases. This major release was also used to cleanup component names as well as generic and port names in interfaces in favor for a unified and clean naming scheme.

Screenshot of the PoC-Library release and the new features

Screenshot: update v3.0.0 and the new features

Watch past Webinars on Demand

PoC-Library part 1

Open-Source VHDL Component Library »Pile of Cores«

Poc-Library part 2

Hands-On: Using Axi4Lite_Register in Vivado

PoC-Library part 3

Solving All CDC Problems with a Handful of Components

PoC-Library part 4

Memory Implementations

PoC-Library part 5

Extending the AXI-4Lite Library

Open-Source VHDL IP Core Library

Open-Source VHDL
IP Core Library